Hi there,
in my current Cyclone V project (5CSXFC6C6U23C8ES) I got one timing analysis setup fail that I just don't fully understand. Therefore, I'm not able to solve this on my own.
I tried different fitter settings which all are failing during timing analysis. I attached the current settings which lead to the best result (just 1 violation with setup slack of -0.004).
I also attached the report file of this setup violation.
My system consits of custom components that are connected to the Leightweight HPS2FPGA bridge. Since I do not see any signals of my custom components in the attached report file, I suppose that there must be something wrong with the AXI->Avalon Interconnect (my custom components all use the Avalon protocol) generated by QSys. Since I have noting to do with this interconnect generation, what can I do to fix that timing violation?
I also added the fitter summary for you to see that the device is far from being "full" so that in my opinion, the fitter should just be able to implement the design correctly....
Thanks,
Maik
