Timing Analyzer - Delay through a pll

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Timing Analyzer - Delay through a pll

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In timing analyzer how does one know the delay from a reference clk input through the pll, clk muxes, etc. to an output pin. I.e. -

[ref clk input pin] --> PLL --> CLK MUX --> [clk out pin]

[Input CLK] ------------------------+

I want to find the phase shift that output clk will have with reference to the two input clks and pll settings. I thought I knew the answer to this but no.

TIA.

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