Timing Closure - Where to start

[Altera_Forum]

Hello All 

I have been handed a large (for me) FPGA design, which seems to have no timing closure, but has just been done.... and when tested on the hardware it appears to work. I have done the tutorials but am still at a loss as to where to start when trying to perform timing closure for this design. Could someone point me at a "Timing closure for Dummies" tutorial which explains things in a little more detail, so i can understand where I get the various params from in the real world.   Thx in advance

[Altera_Forum]

I would start with the Quartus II TimeQuest Timing Analyzer chapter in the Quartus II handbook. If you are unfamiliar with timing analysis concepts, start by reading the Timing Analysis Overview section of this chapter. Then you can get into the tool specific setup.

[Altera_Forum]

When you want to know more about "timing closure" as in how do I optimize the design to meet the timing requirements, refer to the Timing Optimization Advisor in Quartus (see http://www.altera.com/support/kdb/optimization/oa-index.html)