Timing Constraints in DCFIFO through LPM

[skyjuice88]

DCFIFO if generated through IP catalog will have the associated SDC constraints as well (set_max_delay/set_min_delay, set_net_delay and set_max_skew). 

What about DCFIFO instantiated through LPM (https://www.intel.com/content/www/us/en/docs/programmable/772350/23-3/asynchronous-fifo-parameterizable-macro-69581.html)

We use LPM for some of the IPs and would want confirmation if all the constraints are also included in LPM method. 

[RichardTanSY_Intel]

Hi,

There is no associated sdc generated through LPM.

If you choose to code your own dual clock FIFO, you must also create appropriate timing constraints in Synopsis Design Constraints format (.sdc).

Reference: 

https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/dual-clock-fifo-timing-constraints.html

Regards,

Richard Tan

[skyjuice88]

Hi Richard Tan,

The document that you pointed out refers to FIFO that is written through RTL inference. Can I confirm the same applies to LPM instantiation which is using the template provided by Quartus? 

In Quartus --> Edit --> Edit Template --> Verilog HDL --> Intel Parameterizable Macros --> async_fifo

[RichardTanSY_Intel]

Yes, you are right. If you want the SDC to be generated, I would advise using the FIFO Intel FPGA IP to generate the SDC when click the 'Generate HDL.'

Regards,

Richard Tan

[skyjuice88]

Thanks for the confirmation. I have no more question.

[RichardTanSY_Intel]

 I'm pleased to know that your question has been addressed. 

Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan