Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Timing Constraints

Altera_Forum
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Hi,  

 

Could someone please explain timing constraints and how to add them into a design in Quartus. I am a novice and wasn't aware that timing constraints were required to be set by the user? I always thought they were a set of rules/instructions set by the user for the design when it was being synthesized, but in the absence of user defined constraints default criteria would be followed?  

 

Anyway I have a design which I think I should set some timing constrains for, basically in my design I have a clock (so in my constraints I should create a clock?) and two pll clocks derived from the original clock (create two generated clocks?). 

 

Basically in the constraints I want to be able to say any signal that changes with Clock_A for example must have changed its value within (Clock_A period / 2) - a few ns. This I think should ensure that all signals change their value before the next clock edge. 

 

I know what I want to do but I'm not sure how to do it - I've had a look at timequest and some of the documentation online but there are so many contraints settings I don't know what I need to define and what I can leave... 

 

Thanks in advance 

David
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Altera_Forum
Geehrter Beitragender II
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