Timing Optimized VHDL Code

[Altera_Forum]

I'm looking for coding guidelines, rules, online resources, examples, etc. on how to write VHDL code that helps me achieve a higher fmax for my FPGA design. 

 Does anybody have any good recommendations?

[Altera_Forum]

I'm gonna bump up that thread one more time. 

What I had in mind were things like to use certain state machine encodings. I also think I remember reading that counters with many bits make it difficult to reach higher frequencies.  Those are just two examples I came across, not sure if those are really significant. Is there any good literature about that topic?

[Altera_Forum]

http://www.alteraforum.com/forum/showthread.php?t=1025

[Altera_Forum]

Increasing the FMax of a design is all about decreasing the routing delay between two registers. Routing delay is primarily increased by logic (ie. LUTs). If you understand how your code is mapping to logic and registers, then it is simply a case of modifying your code to reduce the logic and adding more pipeline stages. Its not about knowing specific coding examples, as every situation is different. 

 I would suggest understand how your code maps to logic first before reading up how to increase FMax as you will not understand the 2nd problem without understanding the first.

[Altera_Forum]

Ok, so how do I go about checking how my code is mapping to logic and registers? 

 Do you mean looking at actual synthesis results, and if yes, how? Can you direct me to any kind of documentation that explains those concepts?  At this point I never thought past RTL code, besides maybe that a clocked process is something like a flip flop.

[Altera_Forum]

This comes down to fundamental understanding - you're going to have to find textbooks on basic digital logic hardware and read a good VHDL tutorial that shows you the templates for basic elements and shows you designs - I think this often gets good reviews: 

https://www.amazon.co.uk/designers-guide-vhdl-systems-silicon/dp/0120887851/ref=pd_sim_14_3?ie=utf8&dpid=41hoxajjmtl&dpsrc=sims&prest=_ac_ul160_sr116%2c160_&refrid=dh37pjhmb0pwzwt3xz68  But there are many many out there.    --- Quote Start ---   At this point I never thought past RTL code, besides maybe that a clocked process is something like a flip flop.   --- Quote End ---    In a clocked process, every bit of every signal assigned in the becomes a single flip flop. The if/elseif/else statements make the combinatorial logic. So the more layered ifs, the longer the logic chain. (this is a very crude analogy, but you will need to understand what logic your code is generating.  So see the generated output - you need the RTL and map viewers, available in Quartus via Tools->Netlist Viewers.