Timing constraints for SoC HPS SPIM routed through FPGA fabric

[Altera_Forum]

I'm working with a prototype project using an Altera Cyclone V SoC Development kit. We have chosen to route IO pins from one of the HPS SPIMs into the FPGA so that we can put the IOs on the HSMC connector. These IOs don't go into any custom logic, just straight out to a device pin. TimeQuest complains about these IOs being unconstrained.  

 The design seems to work but I'm running it very slow with a SPI data being clocked at 100KHz. I want to ramp this up to 10MHz but I'm worried that the lack of constraints will cause unpredictable operation.   I'm a beginner with TimeQuest. Adding false paths for these IOs makes the TimeQuest complaints go away but doesn't make potential timing issues go away. My thought is that a constraint needs to be added that sets the delay of this group of signals through the FPGA to identical values. I don't know how to express this in the constraints file. Does anyone have any suggestions?  Thanks

[Altera_Forum]

I will try set min/max delay from input pins to output pins. not sure if it is going to be accepted but set max/min input/output delay is likely to be rejected as it is meant for reg to reg path. Just a thought.

[Altera_Forum]

You could try set_max_skew.