Timing constraints for a feedback clock system

[Altera_Forum]

Timing constraints can be tricky... any help in understanding this one is welcome. 

 Please read the word document and take a look at the timing contraints and reports.  The question to me is... why are the results with the feedback scheme worse then the one's without? I would expect that the one with feedback is better because a part of the data path is common (at least very similar) as the clock path.

[Altera_Forum]

Your timing report doesn't look like the diagram. I don't see where/how Sck leaves the FPGA. The one with feedback correctly shows that feedback clock for latching the data, but never shows the clock that launches the data(SCK) leaving the FPGA. 

The .sdc has a generated clock for SCK that looks correct. I'm wondering if you get a warning in TimeQuest about being unable to calculate latency to generated clock? THis occurs when it can't find a connection between the -source and the target. Usually this occurs if there is a ripple-clock(toggle FF?) on the path going out, in which case that register needs a generated clock too.

[Altera_Forum]

Here is the stripped project... and the solution i think. The error was that SCK was not assigned to the output pin, it is needed cause i refer my delay loop from this point! Now the feedback scheme is indeed better then the normal scheme. Unfortunatly margins are still marginal :cry: 

create_generated_clock -name SCK -source -invert    I'm happy to receive comments and thoughts.