Timing constraints for virtual pins

Altera_Forum · ‎04-27-2010

I have a subdesign with virtual pins a global clock and global reset.

entity x is
		port(
			Clk		        					: in std_logic;
			Reset							      : in std_logic := '0';
      Input                   : in  std_logic_vector(31 downto 0);
      RedOut                  : out std_logic_vector(Width-1 downto 0);
      GreenOut                : out std_logic_vector(Width-1 downto 0);
      BlueOut                 : out std_logic_vector(Width-1 downto 0)
		  );
end x;

I want to seperatly compile this design to optimize the code for fitting and routing. How do i constrain the IO of this design? It supposed to be embbed in logic that runs on the same clock... a very simple synchrounous design.

Altera_Forum · ‎04-29-2010

If your <insertcolorhere> Outputs feed other logic, you do not need to constrain them at all. From what I can gather you're trying to cut down on compile times and singling out that partition into a standalone project?

Well, since register to register usually needs no constraining if in same clock domain, simply put a DFF synchronous to your Clk signal in between virtual pins and your core. Quartus will then try to meet timing to and from those DFFs and you can check their states in Signaltap or Simulator. That will represent your design better, than using virtual pins directly.

On another note, I don't think one needs to constrain virtual pins at all, since they're just a placeholder. Without a specific physical place, Q2 cannot give you correct timings anyway.

What CLK speeds are we talking anyways?