Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing model: Slow model 85 doesn't appear

Oscar4
Beginner
332 Views

Hello.

 

I'm triyng to do a Gate Level Simulation of a simple Latch D design and I want to use the Timing model slow 85C but that option didn't appears.

 

It there any way to add it?

 

I´m using Quartus 18.1 and a Cyclone lV E

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3 Replies
SyafieqS
Moderator
320 Views

Hi Oscar.


Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families. Use Timing Analyzer static timing analysis rather than gate-level timing simulation. 


SyafieqS
Moderator
297 Views

Oscar,


May I know if there is any update?


Oscar4
Beginner
237 Views

Hello

 

Thank you four your answer, as you say Gate-level simulation is slow but it was part of a practice, and my problem was that I selected the wrong device family.

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