Hi all!
I'm testing an interface between a CycloneIV fpga and a AD9915 DDS, and I observe random mishaps. This is an extract of AD9915 datasheet:
When DDS is in parallel mode (selected via F[3:0]=0000) the interface is asynchronous and everything works just fine.
When DDS is in direct mode (F[3:]>=0010) data is (should be) synchronous with sync_clock (156MHz, rising edge), but something happens along the way. Sync_clock is sourced by dds and enters a dedicated clock pin into fpga. It's used inside fpga logic to clock two cascaded shift registers (clock domain crossing) , the latter of which is routed to an output pin:
Timequest is telling me that function and data bits arrival time are widespread from 3.8ns (bit19) to 7.2ns (bit26):
report_path -from [get_keepers {dds:dds_inst|ad9915:ad9915_inst|sync_data_out[1][*] dds:dds_inst|ad9915:ad9915_inst|sync_func_out[1][*]}] -to [get_keepers {dds_data[*] dds_function[*]}] -npaths 100 -panel_name {Report Path} -multi_corner -stdout
Report Path: Found 36 paths. Longest delay is 7.260
Path #1: Delay is 7.260
Path #2: Delay is 6.968
Path #3: Delay is 6.694
Path #4: Delay is 5.263
Path #5: Delay is 5.251
Path #6: Delay is 5.179
Path #7: Delay is 5.160
Path #8: Delay is 5.159
Path #9: Delay is 5.149
Path #10: Delay is 5.123
Path #11: Delay is 5.115
Path #12: Delay is 5.044
Path #13: Delay is 4.959
Path #14: Delay is 4.949
Path #15: Delay is 4.931
Path #16: Delay is 4.926
Path #17: Delay is 4.916
Path #18: Delay is 4.899
Path #19: Delay is 4.748
Path #20: Delay is 4.731
Path #21: Delay is 4.719
Path #22: Delay is 4.601
Path #23: Delay is 4.556
Path #24: Delay is 4.553
Path #25: Delay is 4.545
Path #26: Delay is 4.480
Path #27: Delay is 4.469
Path #28: Delay is 4.443
Path #29: Delay is 4.441
Path #30: Delay is 4.432
Path #31: Delay is 4.091
Path #32: Delay is 3.840
Path #33: Delay is 3.835
Path #34: Delay is 3.822
Path #35: Delay is 3.818
Path #36: Delay is 3.799
36 7.260
Is there any means for "equalize" all these timings? I've tried fiddling around .sdc constraints with no changes.
Link Copied
I've tried set_max_delay and set_min_delay, but I can't understand how they work.
#**************************************************************
# Set Maximum Delay
#**************************************************************
set_max_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_data_out[1][*]}] -to [get_ports {dds_data[*]}] 12
set_max_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_func_out[1][*]}] -to [get_ports {dds_function[*]}] 12
#**************************************************************
# Set Minimum Delay
#**************************************************************
set_min_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_data_out[1][*]}] -to [get_ports {dds_data[*]}] 11.5
set_min_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_func_out[1][*]}] -to [get_ports {dds_function[*]}] 11.5
Per my understandings these should tell the fitter to insert some delay to guarantee 12ns of propagation, and match the spread to 500ps, but this is the result:
Delays have increased *a lot*, ranging from 15.5 to 16.5 ns. Neither min_delay nor max_delay have been satisfied.
What am I missing?
Hi,
I miss the constraint set_multicycle_path. This constraint most probably suits your case better. Checks this video (10:53) for further details.
For example before set_multicycle_path (image),
After set_multicycle_path (image),
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
