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Top Design Logic - Where?

Altera_Forum
Honored Contributor II
‎10-08-2010 03:30 PM
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Hi,  

In the niosii_ethernet_standard_3c25 demo project, it does not contain .bdf file. But it can pass the compilation. 

 

I created a similar project. It failed compilation of no top design logic. I am wondering how to add (automatically/programatically generated) top design logic into the system. 

 

Is the .bdf required? 

 

I think I have not assign pins yet. But the Pin planner and Pin assigmentEditor seem not showing steps for auto pin assignments. After passed SOPC generate, the system only generates sdram.ppf, which can automatically imported into pin planner. But what about other pins, such as ethernet/serial/pio etc.? Any document or example that show the steps for auto pin assigment? 

 

Thank you, 

oneplusone
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Altera_Forum
Honored Contributor II
‎10-08-2010 03:57 PM
703 Views

Open the file you want to be the top level entity (bdf or hdl). 

Then go to file menu and select Create symbol files for current file. 

Finally, in project Settings->General select this new symbol as your top level entity.
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