Hello community,I have a question regarding my top-level design which is instanced as a (.bdf)-file. I have several componentes which are implemented in VHDL but they were also created as (.bdf)-files and connected to each other in order to enable a proper interaction. Actually my questions are: 1) Is it possible to use something similar to the "CONFIGURATION"-declartion in your entity to tell your top-level design that specific components are not considered to be synthesized because I actually dont want to use them and save some logics for my design? I mean I could simply remove that instanced components I would not like to use but u would actually need to connect it all over again. For example u can decide if u want to use a simple VHDL Block which is using the CAN-Bus interface or another VHDL-Block which is actually using the SPI interface. Only one of them need to work at a time because the received data protocol has the same structure but different interfaces can be used for testing purposes. 2) Is it possible to set specific generics in one block in my top level design instead of selecting every instanced component in my design and parametrizing its generics? I have seen that its possible to use specific tcl.-scripts, for example: set_parameter -name X_length 136 set_parameter -name Y_data X"0FFF" set_parameter -name Z_length 16 But its not recognized by my top level. Another approach i have faced is that u can go through settings--> defaualt parameters and set specific generics in general. But I would like it to be more visualized in my top level design instead of walking through setting parameters. Kind regards, Sekiba
If you did all the code in vhdl, then you can use generics to enable or disable blocks at compile time via generics. Fibrous can be passed through from graphical files via block parameters I think, but I don't think bdf files instantiated from vhdl can have generics. I highly suggest you ditch the bdf files and stick only to HDL.