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Transceiver Toolkit all tests grayed out

KKuhl1
Novice
357 Views

I have a design on an Aria 10 board (10AX115N3F40E2SG is the FPGA PN)

 

It has 4 SerDes blocks each with 4 bidirectional channels.

 

When I open up the transceiver toolkit from the project the channels get seen and I can map them into Transmitter channels, Receiver channels and transceiver links.  For the Transmit and Receive links I can see the settings and change them and they seem to take effect.  I can also put the links in loopback mode.  I cannot however start any tests.  I suspect the issue is associated with not being able to see the generator or checker.  When I map the transmitter and receiver channels nothing shows up in the checker or generator path pulldowns.

 

I have tried doing builds with both the Enable PRBS soft accumulators  box checked and unchecked with a Altera Avalon Data Pattern Checker and Altera Avalon Data Pattern Generator instantiated

 

First how do I find out of the Aria 10 I am using had the patter generator/checker built in as hard IP FPGA PN is 10AX115N3F40E2SG)

Second how do I get the pattern checker and Generator to show up in the transmit/receiver channels

And third is that even my problem

I am on Quartus Prim 18.1.0 Build 625

Thanks

 

 

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1 Solution
KKuhl1
Novice
298 Views

 

Thanks for the information

 

So I found the solution in the youtube video.  The issue was that the enable capability registers box has to be checked in the Native Phy IP for the toolkit to proper recognize and set up the links to allow the testing to run.

 

I had been using the Intel Technical Training course "Transceiver Toolkit for Intel® Arria® 10 and Cyclone® 10 GX Devices" as a reference for how to set up the IP and it incorrectly shows and does not mention that the capability register box needs to be checked.

https://www.intel.com/content/www/us/en/programmable/support/training/course/otcvrkita10.html

 

Thanks again and problem solved

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3 Replies
Deshi_Intel
Moderator
333 Views

Hi,


The hard PRBS generator and checker design logic is already prebuild in each Arria 10 transceiver channel. You don't need to create additional PRBS generator/checker for it.


What you need to do to enable it is

  1. Enable the correct setting in NativePHY IP
  2. Build simple design to connect all NativePHY IP + PLL IP + PHY reset contoller IP in your top level design file
  3. Compile and program the sof file to Arria 10 FPGA
  4. Ensure JTAG connection is working, your board supply correct clk to NativePHY IP reconfig_clk and also ensure reconfig_reset is not stuck in reset mode
  5. Then launch toolkit and use it


You can refer to transceiver PHY user guide doc (page 623, chapter 9.2. Transceiver Debugging Flow Walkthrough) for more detail usage of toolkit usage guideline


I also found below youtube video that you can check out (there total of 4 video)


Thanks.


Regards,

dlim



KKuhl1
Novice
299 Views

 

Thanks for the information

 

So I found the solution in the youtube video.  The issue was that the enable capability registers box has to be checked in the Native Phy IP for the toolkit to proper recognize and set up the links to allow the testing to run.

 

I had been using the Intel Technical Training course "Transceiver Toolkit for Intel® Arria® 10 and Cyclone® 10 GX Devices" as a reference for how to set up the IP and it incorrectly shows and does not mention that the capability register box needs to be checked.

https://www.intel.com/content/www/us/en/programmable/support/training/course/otcvrkita10.html

 

Thanks again and problem solved

Deshi_Intel
Moderator
295 Views

Good. I am glad that your issue is resolved !


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