Trouble setting signal value <advanced>

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I have made this program as part of an assignment where I'm supposed to design a one bit voter, for micro controllers use in a student satellite. The code works except the part where i am trying to reset the circuit.  

In the sync process i have a signal, clear_input_ok, if this is set to '1' by the reset, the input_ok is supposed to be set to "1111" in the combinatorial process. This doesn't work though, I've asked my TA, and my professor, and they haven't fount a solution, and say that it should work. I will include source code. Thanks in advance!   library IEEE; use IEEE.STD_LOGIC_1164.all; entity Voter is port( CLK : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; reset : in STD_LOGIC; y : out STD_LOGIC; status : out STD_LOGIC_VECTOR(2 downto 0) ); end Voter; --}} End of automatically maintained section architecture Voter of Voter is SIGNAL input_ok: STD_LOGIC_VECTOR(3 downto 0); SIGNAL clear_input_ok: STD_LOGIC; SIGNAL async_status: STD_LOGIC_VECTOR(2 downto 0); SIGNAL result_y: STD_LOGIC; begin sync: process (CLK,reset) begin if reset = '1' then clear_input_ok <= '1'; else clear_input_ok <= '0'; end if; if clk = '1' then status <= "000"; y <= result_y; status <= async_status; end if; end process sync; comb: process (a,b,c,d, clear_input_ok) VARIABLE vote_one : INTEGER RANGE 0 TO 4; VARIABLE vote_null : INTEGER RANGE 0 TO 4; VARIABLE failed : INTEGER RANGE 0 TO 4; VARIABLE result : STD_LOGIC; begin failed := 0; vote_one := 0; vote_null := 0; async_status <= "000"; if (clear_input_ok = '1') THEN report("if statement runs!"); input_ok <= "1111"; end if; ------- inkrements voting variables---------- if (input_ok(0) = '1') THEN if (a='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; if (input_ok(1) = '1') THEN if (b='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; if (input_ok(2) = '1') THEN if (c='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; if (input_ok(3) = '1') THEN if (d='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; ----- figure out result ------ if (vote_one = 4) THEN result := '1'; end if; if (vote_null = 4) THEN result := '0'; end if; -----check if there is contradicting values, and how many? and uppdate failed---------- if (a /= result) OR input_ok(0) = '0' THEN input_ok(0) <= '0'; failed := failed +1; end if; if (b /= result) OR input_ok(1) = '0' THEN input_ok(1) <= '0'; failed := failed +1; end if; if (c /= result) OR input_ok(2) = '0' THEN input_ok(2) <= '0'; failed := failed +1; end if; if (d /= result) OR input_ok(3) = '0' THEN input_ok(3) <= '0'; failed := failed +1; end if; ----- uppdate status------ if failed = 0 THEN async_status <= "000"; end if; if failed = 1 THEN async_status <= "001"; end if; if failed = 2 THEN async_status <= "010"; end if; if failed > 2 THEN async_status <= "111"; end if; ------uppdate result------- result_y <= result; end process comb; end Voter;

[Altera_Forum]

--- Quote Start ---  I have made this program as part of an assignment where I'm supposed to design a one bit voter, for micro controllers use in a student satellite. The code works except the part where i am trying to reset the circuit.  In the sync process i have a signal, clear_input_ok, if this is set to '1' by the reset, the input_ok is supposed to be set to "1111" in the combinatorial process. This doesn't work though, I've asked my TA, and my professor, and they haven't fount a solution, and say that it should work. I will include source code. Thanks in advance!   library IEEE; use IEEE.STD_LOGIC_1164.all; entity Voter is port( CLK : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; reset : in STD_LOGIC; y : out STD_LOGIC; status : out STD_LOGIC_VECTOR(2 downto 0) ); end Voter; --}} End of automatically maintained section architecture Voter of Voter is SIGNAL input_ok: STD_LOGIC_VECTOR(3 downto 0); SIGNAL clear_input_ok: STD_LOGIC; SIGNAL async_status: STD_LOGIC_VECTOR(2 downto 0); SIGNAL result_y: STD_LOGIC; begin sync: process (CLK,reset) begin if reset = '1' then clear_input_ok <= '1'; else clear_input_ok <= '0'; end if; if clk = '1' then status <= "000"; y <= result_y; status <= async_status; end if; end process sync; comb: process (a,b,c,d, clear_input_ok) VARIABLE vote_one : INTEGER RANGE 0 TO 4; VARIABLE vote_null : INTEGER RANGE 0 TO 4; VARIABLE failed : INTEGER RANGE 0 TO 4; VARIABLE result : STD_LOGIC; begin failed := 0; vote_one := 0; vote_null := 0; async_status <= "000"; if (clear_input_ok = '1') THEN report("if statement runs!"); input_ok <= "1111"; end if; ------- inkrements voting variables---------- if (input_ok(0) = '1') THEN if (a='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; if (input_ok(1) = '1') THEN if (b='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; if (input_ok(2) = '1') THEN if (c='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; if (input_ok(3) = '1') THEN if (d='1') THEN vote_one:= vote_one +1; else vote_null:= vote_null +1; end if; else vote_one := vote_one +1; vote_null := vote_null +1; end if; ----- figure out result ------ if (vote_one = 4) THEN result := '1'; end if; if (vote_null = 4) THEN result := '0'; end if; -----check if there is contradicting values, and how many? and uppdate failed---------- if (a /= result) OR input_ok(0) = '0' THEN input_ok(0) <= '0'; failed := failed +1; end if; if (b /= result) OR input_ok(1) = '0' THEN input_ok(1) <= '0'; failed := failed +1; end if; if (c /= result) OR input_ok(2) = '0' THEN input_ok(2) <= '0'; failed := failed +1; end if; if (d /= result) OR input_ok(3) = '0' THEN input_ok(3) <= '0'; failed := failed +1; end if; ----- uppdate status------ if failed = 0 THEN async_status <= "000"; end if; if failed = 1 THEN async_status <= "001"; end if; if failed = 2 THEN async_status <= "010"; end if; if failed > 2 THEN async_status <= "111"; end if; ------uppdate result------- result_y <= result; end process comb; end Voter;   --- Quote End ---    you must be updating input_ok back to zeros on last statements in the comb process. Remember it is sequential process and last statements overwrite.

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TO_BE_DONE

[Altera_Forum]

Thank you for reply. I will take your advice and start over again.