Trouble with register packing in DSPs

[Steven_H]

I'm developing a utility with MATLAB - HDL Coder to characterize DSP mapping behavior and timing with Intel devices. However, I noticed some strange behavior compared to Xilinx/AMD devices.

I thought with Quartus Prime Pro (targeting Stratix 10) the preference was to have synchronous resets on registers now, but synchronous reset registers do not get packed into DSPs. Instead, asynchronous reset registers do.

Additionally, registers with clock enable signals (clock gating) do not get packed into DSPs. This is not a problem with Xilinx/AMD devices.

I've attached two zip files with synthesis TCL scripts to observe when registers get packed (without_ce.zip) vs when registers aren't packed (with_ce.zip). The script can be run with the command "quartus_sh -t Synthesis.tcl".

I prefer to ensure these registers are packed in a DSP (in BlockSubsystem.vhd) while also having optimal behavior when they are not packed (like the registers in toplevel_Characterization.vhd).

1. Is this all expected behavior?
2. What is the general guidance when using both Quartus Prime Standard and Quartus Prime Pro? Or are there even finer differences based on the device family?

Thanks,

Steven

[TingJiangT_Intel]

Hi there, if you want your logic be inferred to DSP, you need to follow some coding style recommended.

Please follow the following steps to get the template:

1,You can open Quartus, create a new Verilog HDL file.

2,Right click on the blank area and choose 'insert template'

3,In the opened window choose 'Verilog HDL' -'Full design' - 'Arithmetic' - 'DSP Feature' - Choose Corresponding Template you need.

Please check if your code follows this coding style.

Thanks

[TingJiangT_Intel]

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