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I'm pretty new to using modelsim. I have a really simple design with just a PLL, and I wanted to test it using modelsim. However, when I try to run the simulation I get an error stating the following:
Error: (vsim-3033) D:/altera/11.0/testproject/testpll_syn.v(141): Instantiation of 'testpll_altpll' failed. The design unit was not found. I guess I'm missing something in my library? I'm pretty lost so if someone could point me in the right direction I'd really appreciate it.Link Copied
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I assume that you're simulatin using Modelsim and a testbench.
Are you sure the you instantiate design to be simulated using the verilog name otf the file that contains the PLL? Do you have in you design directory the files: altpll0.v altpllo.qip etcetera?- Mark as New
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Yes, I have all those files in my design directory. And I'm pretty sure its being instantiated correctly.
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Should be something simple.
Can you devise what testpll_altpll is? Is it the top level entity of your design? Can you upload your testbench and the files that describe your design?
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