Two Clock Inputs questions for VHDL

[Altera_Forum]

I have a process that needs to be run off two clocks (shifting Bits) When clk1 changes state and clk2 is low i should shift ALSO when clk2 changes state and clk1 is low i should shift. 

 I am having an issue getting that logic to work right in VHDL can someone assist me ? I have the code below but it does not update X and Y correctly i am trying to use Z to run the Shift Process. But its like it will not update the X and Y values properly.   process(CPIN,CPINH) BEGIN if ((CPIN'EVENT and CPIN = '1' )and CPINH = '0') then X <='1'; ELSIF ((CPIN'EVENT and CPIN = '1' )and CPINH = '1') then X <='0'; END IF ; end process; ---------------------------------------------- PROCESS(CPIN,CPINH) BEGIN If ((CPINH'EVENT and CPINH = '1' )and CPIN = '0') then Y <='1'; ELSIF ((CPINh'EVENT and CPINH = '1' )and CPIN = '1') then Y <='0'; END IF ; END PROCESS; --------------------------------- process(X,Y) BEGIN Z<= X XOR Y; end process; ------------------------ process(Z) BEGIN if (Z = '1') then --DO STUFF end process

[Altera_Forum]

This is quite the ugly problem. I think more information is needed to recommend how to help. 

 CPIN and CPINH: Are these clocked inputs?  What is the maximum toggle rate of your inputs? Do you have any actual clocks available in your design? If so, what speed(s)? If both CPIN and CPINH have the same maximum toggle rate, is the phase relationship between the two known?  Side note: "Z <= X XOR Y;" does not need to be wrapped in a process. It can stand alone and will generate as you would expect.

[Altera_Forum]

--- Quote Start ---  This is quite the ugly problem. I think more information is needed to recommend how to help.  CPIN and CPINH: Are these clocked inputs?  What is the maximum toggle rate of your inputs? Do you have any actual clocks available in your design? If so, what speed(s)? If both CPIN and CPINH have the same maximum toggle rate, is the phase relationship between the two known?  Side note: "Z <= X XOR Y;" does not need to be wrapped in a process. It can stand alone and will generate as you would expect.  --- Quote End ---    CPIn and CPINH are controlled by debounced switches, this is for a lab project and i am trying to figure out this last part i need to figure out. so if i clock cpin and cpinh is low then it shifts..... so if i clock cpinh and cpin is low then it shifts..... this shifting is controlled by a process that runs off when Z changes states the xor is there for when CPin changes it controls X when CPinh changes it controls y if X and Y are 0 nothing happens if X and Y are 10 or 01 shift -- this is why the XOR is needed generates a one on both of these conditions if X and Y are 11 or 11 nothing happens

[Altera_Forum]

basically, you cannot use two clocks in FPGAs (nothing wrong with it in VHDL, but it doesnt map to any real hardware). 

I suggest you run a master clock and synchronise everything to it.

[Altera_Forum]

Well they do not run at the same time so if both are HIGH nothing happens but : 

if CPIN goes HIGH while CPINH is LOW then clock Z if CPINH goes HIGH while CPIN is LOW then clock Z and that is the only time something should happen because Z should be LOW unless one of the two things above happens this clock runs a process that shifts bits. i have tried the code below and while it simulates what i want to happen i am not sure if i have a hardware issue or  or if its still in software.   process(CPIN,CPINH) BEGIN if ((CPINH = '0' ) OR (CPIN = '0' ))then if (CPIN = '1'OR CPINH = '1')then Z <='1'; ELSE Z<= '0'; END IF; END IF; end process;

[Altera_Forum]

It looks like you have created an XOR gate. (Z <= CPIN XOR CPINH;) I'm not sure if this is the desired behavior. 

 If your initial description is correct, I agree with Tricky - use a master clock to synchronize your behavior. Something like:  PROCESS(CLK, RESET) BEGIN IF (RESET = '1') THEN cpin_reg_s <= '0'; cpinh_reg_s <= '0'; cpin_reg1_s <= '0'; cpinh_reg1_s <= '0'; ELSIF (rising_edge(CLK)) THEN --register your inputs to prevent timing issues cpin_reg_s <= CPIN; cpinh_reg_s <= CPINH; --remember what last register states were cpin_reg1_s <= cpin_reg_s; cpinh_reg1_s <= cpinh_reg_s; --make decision to do stuff Z <= (cpin_reg_s AND (NOT cpin_reg1_s) AND (NOT cpinh_reg_s)) OR (cpinh_reg_s AND (NOT cpinh_reg1_s) AND (NOT cpin_reg_s)); END IF; END IF; END PROCESS;  Be sure that your clock is significantly faster than your maximum input transition rate.