Unable to find the User Guide document for "dma_read_master" version 19.2.0

[Ashish_Pradhan]

Hello,

  I am unable to find the user guide for dma_read_master ( Version 19.2.0 ). The below link which is provided in the tool seems to be not opening.

https://documentation.altera.com/#/link/dmi1420813268955/dmi1421419198649

Can somebody pls provide the user guide, I need it for correct field mapping for command_sink channel.

Thanks,

Ashish

[KennyTan_Altera]

Do you mean the DMA controller? If yes, if this guide is sufficient?

https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/dma-controller-core.html

[Ashish_Pradhan]

Hi Kenny Tan,

 Thanks for your reply. 

 The DMA core is separate IP and hence these field descriptions does not suit.

"dma_read_master" (Read Master Intel FPGA IP)  and "dma_write_master" (Write Master Intel FPGA IP) are two sub-core of modular Scatter Gather DMA.  The user guide which is available for mSGDMA, and their field description seems not working for the above two mentioned IPs.   So could you pls provide the document which the tool points to the link mentioned in the earlier post . I need to configure its "command_sink" channel.

Thanks & Regards,

Ashish.

[KennyTan_Altera]

Hi Ashish,

Understood, this appear to be a bug on the documentation broken.

Will get back to you on this.

Best regards,

Kenny Tan

[Aflop]

Any word on this? It would help me as well. 

[KennyTan_Altera]

Hi,

There are no update from our developer yet, I will continue to follow up and let you know if I have.

Thanks

[KennyTan_Altera]

We manage to retrieve the UG, can you check your email for this?

We will fix this in the future release of Quartus Prime for the broken link.

[Ashish_Pradhan]

I got it. Thank you very much Mr Tan.  

[KennyTan_Altera · Accepted solution]

Do you have further queries? If no, we shall close this case.

[Kassen]

Hello,

I am also unable to access the user guide for dma_read_master, but for version 23.1. Here's the link:

https://documentation.altera.com/#/link/dmi1420813268955/dmi1421419198649

I believe it is the same link as in the post. So, could you please provide the UG for me as well. 

Thank you

[Kassen]

I actually also need UG for "dma_write_master" (Write Master Intel FPGA IP), which is also a sub-core of modular Scatter Gather DMA, mentioned earlier by Ashish.

The broken UG link of this IP:

https://documentation.altera.com/#/link/dmi1420813268955/dmi1421419198649

Thank you

[KennyTan_Altera]

Hi Kassen,

can you create a new post on this?

Currently, we do not send to public here until our internal team validate the content and fix the Quartus gui.

[KennyTan_Altera]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.