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Altera_Forum
Honored Contributor I
1,268 Views

Unable to synthesize the design with Macros and header files due to undefined Macros

Hi, 

 

I have a design with some Macros and these are being used in multiple files. These Macros are defined in the header file <Macro_defs>.vh. I have added the <Macro_defs>.vh file in my Quartus Project and is being saved as “set_global_assignment -name VERILOG_INCLUDE_FILE ../verilog/<Macros_def>.vh”. But still, the synthesis tool reports the warning as “Critical Warning(13432): Verilog HDL Compiler Directive warning at <verilog_file>.v(64): text macro "Macro_Name" is undefined” and later ends due to errors because of this. 

 

1. I am able to fix this issue by, including the header files in those design files where Macros are being used. But since the design is huge, I cannot include header files in all the files. What are the other possible ways to fix this issue? 

2. Also, what is the exact purpose of “VERILOG_INCLUDE_FILE” in the above set_global_assignment? 

 

Thanks, 

Poorna
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5 Replies
Altera_Forum
Honored Contributor I
95 Views

I think you do need to specifically reference/include the info. It's my understanding that the scope of something included is dependent on the synthesis engine, and therefore risky. I believe the whole `include is being deprecated, or recommended not to be used, and packages should be recommended instead. For example, if you have a typedef, wrap it in a package in classes.sv

package classes; 

typedef enum logic[4:0] { 

FIRMWARE, 

LOC_MMR, 

LOC_LA, **  

LEG_IOH, 

IOAPIC,*******}  

t_class; 

endpackage : classes 

 

In the file that uses it, there no longer is a `include that has to point to the location of the file and is therefore dependent on directory structure. Instead just do: 

 

//No longer use this:`include ../somedir/librs/classes.sv 

import classes::* 

module lower ( 

input coreclk, 

input hemi_select, 

input kti_addr, 

input t_class bike, 

 

Now this file can be added anywhere and it doesn't have to maintain a pointer to the package, nor does it rely on whether the synthesis treats included info as global or not. 

 

(I'm somewhat new to this, so just passing along what I've heard...)
Altera_Forum
Honored Contributor I
95 Views

And I think users would name a file that was included "somename.inc", which didn't really indicate it was Verilog. I'm guessing that's what the assignment was used for, to add it as Verilog.

Altera_Forum
Honored Contributor I
95 Views

Hello Rysc, 

 

Thank you very much for the explanation. 

 

What exactly is the purpose of "VERILOG_INCLUDE_FILE" then? It doesn't seem to work at all. I do not find much information on this anywhere?
Altera_Forum
Honored Contributor I
95 Views

I think it just adds the file to the project. It doesn't treat it in any special way, like making it a global or anything like that. I think it's for when users create a file with a .inc extension, and want it to be added/read as a Verilog file, which used to be pretty common. (Now I see users doing more of <name>_pkg.sv)

Altera_Forum
Honored Contributor I
95 Views

Hello Rysc, 

 

Ok. I got it. Thank you very much again.