Unable to view Platform Designer generated IP interface and internal signals in Questa Simulation.

[Ashish_Pradhan]

Hello,

I am trying to simulate a RTL design which contains a modular scatter gather DMA (stream to memory-map) IP generated by Quartus Prime Pro platform designer.

- I am able to generate HDL from the platform designer and instantiate it in my test bench.
- I am able to generate Simulator setup Script for IP (for Questa simulator) using GUI without any error / warnings.

While trying to simulate the design (using Quartus Tools -> Run Simulation -> RTL Simulation option), Simulation is running without error. I can see module instances inside the Questa simulator (QuestaIntel FPGA Edition Edition-64 2024.1). But unable to see any interface signals to/from the platform designer generated IPs  in the waveform.  I can see all the test bench signals and their transitions in the waveform.

Can anybody suggest where I am going wrong or modifications required (if any) to "run_msim_rtl_verilog.do" file ?

Regards,
Ashish.

[ShengN_Intel]

Hi,

In Questa, you may go to Simulate -> Design Optimization -> Visibility -> Apply full visibility check screenshot:

Or add set USER_DEFINED_ELAB_OPTIONS -voptargs=+acc in run_msim_rtl_verilog.do file then re-execute the .do file

Thanks,

Regards,

Sheng

[ShengN_Intel · Accepted solution]

Hi,

May I know do you have any further concern?

Thanks,

Regards,

Sheng

[Ashish_Pradhan]

Hello ShengN,

 Thanks for your suggestion. I am able to simulate it now.

 But I observe following problem:

I am trying to simulate an Avalon modular scatter gather DMA (msgdma_0) in Stream to memory map configuration. 

 I am trying to send descriptor info (providing write address in appropriate field as specified in the user guide, appropriate Byteenable, 
& Driving "write" signal high from test bench to the DUT (i.e msgdma_0), through the descriptor channel (msgdma_0_descriptor_slave_write, *_descriptor_slave_writedata, *_descriptor_slave_byteenable).

I am also driving data and valid through "msgdma_0_st_srink_data", "msgdma_0_st_srink_valid" and feed to the DUT(msgdma_0),  configured CSR field as per uer guide.

Simulation is running properly without any error, I can see all the test bench signals in the waveform as expected.

But I do not see any output coming out from the platform designer generated IP (msgdma_0) in their respective output ports such as (msgdma_0_mm_write_address, *_mm_write_write, *_mm_write_byteenable, *_mm_write_writedata, or *_csr_irq_irq).

Can you pls guide where I am going wrong ? or suggest how can I get the expected behavior of Avalon modular scatter gather DMA.

Thanks,

Ashish.

[ShengN_Intel]

Hi,

You may go to Questa sim tab -> right-click the instance -> Add to -> Wave -> All items in region and below

Thanks,

Regards,

Sheng

[Ashish_Pradhan]

Hello Sheng,

 Thanks for the reply.  Actually my issue is I am unable to see any transition in those out put channels  which I mentioned in the previous reply. I can see the channels (msgdma_0_mm_write_address, *_mm_write_write, *_mm_write_byteenable, *_mm_write_writedata, or *_csr_irq_irq) in the waveform window.

To brief the problem:

-I exported CSR, descriptor, st_srink, & mm_write channels.  Configure CSR and Descriptor through test bench, & driving data through  st_srink, which I can see in the waveform, but I do not see any transition in the msgDMA   mm_write output channel.

So could you pls guide me where I am going wrong , and how should I'll able to transfer data in msgDMA in a stream to memory-map configuration ?

Thanks & Regards,

Ashish

[ShengN_Intel]

Hi,

Since there's a new post on the another problem. I'll reply in that post instead.

Thanks,

Regards,

Sheng