Unconstrained Clocks

Altera_Forum · ‎08-14-2012

When I view the TimeQuest Timing Analyzer - Unconstrained Paths Summary, 4 Unconstrained Clocks appear. The 4 unconstrained nets should not be clocks, but they are being flagged by the tool. How do I remove these nets as appearing as clocks?

Altera_Forum · ‎08-14-2012

You're using them to drive registers' clock port.

Ie, you have something like it.

process(some_signal) begin
if rising_edge(some_signal) then
...
end if;
end process;

Most of the time, you'll want to change your design not no do that.

Altera_Forum · ‎08-14-2012

I've never seen it report a clock that wasn't being used as one. If I don't know what it's driving, I do a quick:

create_clock -period 1.0 -name test [get_keepers {}]

(It may be get_ports, or something like that). Then just report_timing to that new clock.

The report is there to help you. There is nothing in .sdc to say, I'm not a clock, you just choose not to constrain it. The Unconstrained Paths report is outside of .sdc constraints, and really just trying to help you identify possible mistakes. I would ignore it if it is a clock and you just don't want to constrain it.

(A final option is to put a clock constraint on it that's 1000.0 ns, then do:

set_false_path -to [get_clocks test_clk]

set_false_path -from [get_clocks test_clk]

It should get rid of the info message since it's constrained, and it wont' be analyzed.

Altera_Forum · ‎08-14-2012

You can also use "derive_clocks -period 10.0" to create the clock for you, and then just report timing to the clock that is created that is driving the clock pin in question.

Altera_Forum · ‎08-14-2012

Good point.