Unconstrained Paths errors

Altera_Forum · ‎11-29-2010

Hi all,

I'm having problems with my design Cyclone III with MT48LC4M32B2-7 sdram. I'm new to TimeQuest Analyzer, Clock Phase Shift settings, or Tco, Tpd. Hope someone could help me out to point out problems.

Since my project is over 22MB, so I put it on megaupload site.

Here is the link to the project.

http://www.megaupload.com/?d=cdzeanvj

Best regards,

Sean

Altera_Forum · ‎11-29-2010

If you archive your project (Project->Archive Project)you get a very small file, but with all necessary files with it, like local user and other files outside the project directory path.

And the megaupload site makes one wait 45 seconds before the download start, trying to stuff silly adverts down one's throat. Life's too short ...

Altera_Forum · ‎11-29-2010

Thanks. I just got the qar zip file. It's only 2mb size.

Sean

Altera_Forum · ‎11-30-2010

Have you read the datasheets about how to work with the controller? If you work with the SOPC builder it generates a contraints (sdc) and .tcl file for you.

You can find all the info you need in a datasheet like this (I don't know which controller you use):

http://www.altera.com.cn/literature/ug/ug_ddr_ddr2_sdram_hp.pdf

Altera_Forum · ‎11-30-2010

Hi,

I'm using SDR MT48LC4M32B2-7 memory with Cyclone III. In SOPC Builder, I select SDRAM Controller and default to Micron MT48LC4M32B2-7. For my system clock, I pick 50mhz and same with SDRAM clock in PLL.

Now, the phase shift that I already tried -3.5ns, -3.0ns, -2.0ns , -72deg.... but no luck.

Thanks,

Sean