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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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University VWF won't work

gardo
Beginner
949 Views

This is not a liscence issue and I've run it in admin mode to no avail. University VWF file won't  analyze logic. Won't even give me a reason for the error. I noticed that the path for the last file it's trying to use is obviously invalid as it implies a folder with no name in the specified path. I've also messed with the simulation eda tool settings with no luck. This error happens the same way in Logic and Timing analysis. This is for 21.1 Quartus Prime Lite Edition.

 

 

Determining the location of the ModelSim executable...

Using: c:/intelfpga_lite/21.1/questa_fse/win64/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off ClockProject -c ClockProject --vector_source="C:/intelFPGA_lite/21.1/quartus/bin64/Waveform.vwf" --testbench_file="C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/Waveform.vwf.vt"

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition

Info: Copyright (C) 2022 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Tue Jan 17 19:41:05 2023

Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off ClockProject -c ClockProject --vector_source=C:/intelFPGA_lite/21.1/quartus/bin64/Waveform.vwf --testbench_file=C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/Waveform.vwf.vt

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

 

Completed successfully.

Completed successfully.

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/" ClockProject -c ClockProject

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition

Info: Copyright (C) 2022 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Tue Jan 17 19:41:07 2023

Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/ ClockProject -c ClockProject

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Info (204019): Generated file ClockProject.vo in folder "C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim//" for EDA simulation tool

Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning

Info: Peak virtual memory: 4727 megabytes

Info: Processing ended: Tue Jan 17 19:41:08 2023

Info: Elapsed time: 00:00:01

Info: Total CPU time (on all processors): 00:00:01

 

Completed successfully.

**** Generating the ModelSim .do script ****

C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/ClockProject.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

c:/intelfpga_lite/21.1/questa_fse/win64//vsim -c -do ClockProject.do

Error.

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9 Replies
RichardTanSY_Intel
943 Views

Could you shared the project .qar file so I could try to duplicate the issue from my side?

You may try to restore the simulation setting to default, in the vwf.


I have a feeling this might be a bad installation.

Could you try with a different machine and see if the issue occurs.


Best Regards,

Richard Tan



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engtjm
Beginner
883 Views

Hi Richard,

 

I have the same issue, I have just installed the v21.1 Lite version and this is my first attempt at simulation. The transcript from the simulator is below, and my archive file is attached. 

Thank you in anticipation for your help.

Tim Mulroy 

 

Determining the location of the ModelSim executable...

Using: C:/intelFPGA_lite/21.1/questa_fse/win64

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source="C:/Users/engtj/Quartus/decoder2/Waveform.vwf" --testbench_file="C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt"

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition

Info: Copyright (C) 2022 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Tue Jan 24 15:06:29 2023

Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source=C:/Users/engtj/Quartus/decoder2/Waveform.vwf --testbench_file=C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

 

Completed successfully.

Completed successfully.

**** Generating the timing simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/engtj/Quartus/decoder2/simulation/qsim/" decoder2 -c decoder2

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition

Info: Copyright (C) 2022 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Tue Jan 24 15:06:30 2023

Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory=C:/Users/engtj/Quartus/decoder2/simulation/qsim/ decoder2 -c decoder2

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.

Info (204019): Generated file decoder2.vo in folder "C:/Users/engtj/Quartus/decoder2/simulation/qsim//" for EDA simulation tool

Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings

Info: Peak virtual memory: 4657 megabytes

Info: Processing ended: Tue Jan 24 15:06:30 2023

Info: Elapsed time: 00:00:00

Info: Total CPU time (on all processors): 00:00:01

 

Completed successfully.

**** Generating the ModelSim .do script ****

C:/Users/engtj/Quartus/decoder2/simulation/qsim/decoder2.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

C:/intelFPGA_lite/21.1/questa_fse/win64/vsim -c -do decoder2.do

Error.

 

0 Kudos
RichardTanSY_Intel
919 Views

May I know does my latest reply/suggestion helps?


Best Regards,

Richard Tan


p.s. Please do expert delay in response due to lunar new year. 


0 Kudos
RichardTanSY_Intel
862 Views

Hi @engtjm 


You are running timing simulation in your vwf. "Run Functional Simulation" works fine.

Use timing analysis tool in the Quartus tool instead.

 

Best Regards,

Richard Tan

 

0 Kudos
engtjm
Beginner
852 Views

Hi Richard,

I have tried to run the functional simulation in the University Program VWF, and I get the same error. Please see below.

With best regards, Tim

Determining the location of the ModelSim executable...

Using: C:/intelFPGA_lite/21.1/questa_fse/win64

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source="C:/Users/engtj/Quartus/decoder2/Waveform.vwf" --testbench_file="C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt"

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition

Info: Copyright (C) 2022 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Fri Jan 27 16:38:15 2023

Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source=C:/Users/engtj/Quartus/decoder2/Waveform.vwf --testbench_file=C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

 

Completed successfully.

Completed successfully.

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/engtj/Quartus/decoder2/simulation/qsim/" decoder2 -c decoder2

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition

Info: Copyright (C) 2022 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Fri Jan 27 16:38:17 2023

Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/Users/engtj/Quartus/decoder2/simulation/qsim/ decoder2 -c decoder2

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Info (204019): Generated file decoder2.vo in folder "C:/Users/engtj/Quartus/decoder2/simulation/qsim//" for EDA simulation tool

Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning

Info: Peak virtual memory: 4649 megabytes

Info: Processing ended: Fri Jan 27 16:38:17 2023

Info: Elapsed time: 00:00:00

Info: Total CPU time (on all processors): 00:00:01

 

Completed successfully.

**** Generating the ModelSim .do script ****

C:/Users/engtj/Quartus/decoder2/simulation/qsim/decoder2.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

C:/intelFPGA_lite/21.1/questa_fse/win64/vsim -c -do decoder2.do

Error.

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RichardTanSY_Intel
816 Views

I am not able to duplicate the issue that you seen. The nativelink simulation all just works fine from my side with 21.1 and 22.1 lite/std version.

 

Not sure if this could be due to the VC redist package problem.

Try uninstall VC 2015-2019 first, then install the latest from:

https://learn.microsoft.com/en-US/cpp/windows/latest-supported-vc-redist?view=msvc-170

 

If issue still persists, could you try to reinstall Quartus with the .tar file (5.5GB) and install with admin. Then, run the Quartus with admin privilege?

Try to temporarily disable the antivirus software during the Quartus Prime software download and installation process.

 

Quartus v22.1 lite .tar file download link:

https://www.intel.com/content/www/us/en/software-kit/757262/intel-quartus-prime-lite-edition-design-software-version-22-1-for-windows.html

 

Do you also observe the same issue in other machine?

Which OS are you using? 

 

Best Regards,

Richard Tan

 

 

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RichardTanSY_Intel
786 Views

Hi @engtjm 


Do you able to proceed with the simulation? If University VWF is still not working, I suggest to use the Nativelink simulation flow for now.

You can create your own testbench or generate the testbench from VWF.


Best Regards,

Richard Tan


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RichardTanSY_Intel
777 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. 


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.



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engtjm
Beginner
757 Views

Hi Richard,

Thank you for your help, and I will try out your suggestions.

Tim Mulroy

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Reply