Upsampling QPSK Symbols

Altera_Forum · ‎02-20-2015

I am trying to implement QPSK modulator in FPGA using Verilog.

I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1

I channel will be: 1 1 0 0 and Q channel will be: 0 1 1 1

Now I need to upsample these two channels, assume I want to upsample by 8, does it mean that I change the "width" of each bit to 8? i.e. I channel will be: 00000001 00000001 00000000 00000000 and Q channel will be: 00000000 00000001 00000001 00000001

Or I just repeat each bit 8 time? i.e. I channel: 11111111 11111111 00000000 00000000 and Q channel: 00000000 11111111 11111111 11111111

After using the correct way of upsampling, how do I map ones and zeros to 1 and -1?

Altera_Forum · ‎02-20-2015

You need to map I and Q raw binary values to constellation signal levels (of your system, DAC). That depends on your mapping to constellations.

e.g. if IQ pair is 00 is in first quadrant then map to I => +1000, Q => +1000

Then you apply upsampling using filter on the mapped values (raw data gone now).

In some cases, both mapping and upsampling (and possibly shaping) is done internally in the filter which will use raw binary values as inputs.

Altera_Forum · ‎02-20-2015

Thanks Kaz for your reply.

Good to know something, but you triggered another questions if you don't mind :)

1- Do you mean that mapping values (+1000) changes according to DAC?

2- How does DAC relate to I and Q signals? They will be modulated with carriers, right?

3- And you didn't answer my question about upsampling and how it goes :)

4- One more thing, in regard to the last point of mapping, upsampling and shaping... is Raised Cosine filter one of these filters?

Altera_Forum · ‎02-20-2015

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1- Do you mean that mapping values (+1000) changes according to DAC?

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The DAC dynmaic range is the ultimate digital point. So you make most of that range.

You have constellations at +/-1 for I/Q (normalised) you then scale it to DAC resolution

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2- How does DAC relate to I and Q signals? They will be modulated with carriers, right?

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carrier modulation is system option. you can send your I/Q into separate DACs then modulate in analogue world.

or you can do some lifting from baseband inside digital domain

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3- And you didn't answer my question about upsampling and how it goes

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use filter for upsampling. This is a bit involved area, basically you apply interpolating filter

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4- One more thing, in regard to the last point of mapping, upsampling and shaping... is Raised Cosine filter one of these filters?

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yes when you implement as such i.e. as mapper, channel shaping and upsampler

and it does not need any mults in this case as you have few signal levels so you get your mutiplication pre-done in LUTs.

I know you need more details but what can I do?

Altera_Forum · ‎02-20-2015

I appreciate your help, thanks a lot. Actually yes I am still confused so I hope you answer my questions :)

I want to design the whole system in FPGA, so my DAC will produce the RF signal. I have already done FM modulation and now I am working to implement QPSK.

1- I still can't understand why do I need to scale I/Q to DAC resolution? (By the way, does the +1000 represent a DAC resolution in your example?) After mapping I/Q I will multiply them with carriers then sum both arms (I/Q channels) then send the modulated carriers to DAC (Digitally speaking), I think here lies my confusion with what you suggested in the first point in the previous reply.

2- Do you recommend using RRC to handle all of that? I have made a literature review and come out with the attached block diagram.

Altera_Forum · ‎02-20-2015

In short yes an RRC filter can handle mapping, shaping and upsampling. The mixer is then applied at high sample rate.

The RRC filter will imply scaling as well.

start with say 80 coefficients (depends on baseband width), split up into 8 polyphases e.g. polyohase1 = coeffs(1:8:end)

polyphase 2 = coeffs(2:8:end)

since you will multiply these by +1 and -1 then you just store coeffs and add up the sum of coeffs (inverting if input stage = -1)

You run a counter 0~7 as polyphase pointer. and input delay line of 10 stages

at count0 you add up sum of coeffs for polyphase1 => first output

count1 add up those of polyphase2 => second output and so on

...

at count7 end advance the input stage once and repeat sums

That is all !the output will come out 8 samples for every input advance, nice and smooth ready for mixining

Altera_Forum · ‎02-20-2015

Note the coeffs have to be scaled to DAC resolution

Altera_Forum · ‎02-21-2015

That sounds brilliant! Can you please provide me with a quick example of scaling coeffs to DAC resolution?

Now just to make sure that I understand the other method (not using a single filter to do it all), I am going to describe how it should be and you tell me if I am right or wrong.

Taking the diagram I attached as a reference:

1- Mapping block will map I/Q to 1 and -1. (If I'm right, how wide this should be?)

2- I think after this stage I need to up-sample by 8 or so. (To the best of my knowledge, this is slightly different from interpolating which invloves filtering)

3- RRC filter will change the shape of the square samples to something more curved. (I don't know it is going to increase the sample rate, i.e. upsample)

4- Interpolate by upsampling (inserting zeros) and filtering, to accomodate mixer rate.

5- Finally upconvert to RF using mixers.

Altera_Forum · ‎02-21-2015

scaling: DAC resolution 11 bits signed

coeffs = round( 1023* coeffs/max(coeffs));

Regarding your steps:

mapping is straight forward with qpsk (1 => 1, 0 => -1 or the reverse)

upsampling: You are mixing up between upsampling term used by two sets of people. DSP upsampling is achieved by interpolation.

You can if you wish add zeros e.g. one sample followed by 7 zeros then apply filter.

this is physical zero insertion prior to filtering but it will waste resource as you can assume zeros then filter according to polyphase approach.

if you instead of zero insertion repeat the values it will I believe add massive dc

So to follow your plan:

map => assume zeros => apply RRC (requires up2 at least) => mix => DAC

it ended up same as I first described with polyphase structure.

It will help you if you can model in matlab your chain. Just like modelsim helps with usual logic.

Altera_Forum · ‎02-21-2015

It's amazing when you understand something :D Thanks a lot Kaz

I've just discovered the charm of RRC filters in MATLAB :D

One more thing (I hope it's the last and I won't bother you anymore :) )

I think I'm going to take it your way so...

What determine number of coeffs?

And can I design the RRC filter and calculate the coeffs and just insert them in Altera FIR Compiler? or it has a special structure?

Altera_Forum · ‎02-21-2015

rrc design is pretty standard.

number of coeffs is based on your upsampling rate chosen, passband ripple and stopband attenuation required.

for example:

To design root raised cosine filter with 70 taps, set F[SUB]C[/SUB] to 0.25 with respect to F[SUB]S[/SUB] of 1 and assume rolloff of 0.18

h = firrcos(69, 0.25, 0.18, 1, ‘rolloff’, ‘sqrt’);

The chosen Fc implies that upsampling by 2 is to be applied. Fc is cutoff, Fs is sampling rate (normalised)

You can use fir compiler and is best choice as it can do upsampling as well. (though it does not support LUT approach and will use few mults)

edit: transition band is also significant and is controlled by alpha for a given number of taps.

Altera_Forum · ‎02-21-2015

Thanks Kaz.

How could you tell that Fc implies upsampling by 2?

So all I have to do is to design the filter in MATLAB, calculate coeffs and feed them to FIR compiler.

PS: In your previous reply when you gave example about DAC resolution, have not you should say: coeffs = round(2023* coeffs/max(coeffs)); as the DAC has 11 bits?

Altera_Forum · ‎02-21-2015

11 bits signed (dynamic range = +/- 1023), one bit is sign bit

rectangular symbols contain infinite frequencies. You plan to pass minimum bandwidth without losing information.

The rule of not losing information is that you pass a bandwidth from 0 to half Rs (symbol rate).

Your Fs to begin with is = Rs so you need to pass 0.5 Fs bandwidth

Then you require minimum upsampling of 2 thus your filter will have to work at 2 *Rs speed and cutoff at same point of 0.5 Rs

in other words if Fs is 1 then Fc becomes 1/4 (= 2/0.5)

Altera_Forum · ‎02-21-2015

OMG!! Thanks a Million Kaz!!! I got it now!

I hope someday I will get quarter of your expertise :D

Thanks again... I appreciate your help.