Urgent VHDL Comparator

[Altera_Forum]

Can some one please tell me whats wrong with my code (check attached document). I'm designing a comparator to compare two input bit (A and B). But input B is supposed to be a reference with a fixed value of 8192 (10000000000000). Pls attached a code to comment (Structural). thank you

[Altera_Forum]

hi, 

Delete the line "B = data;" : no sense and must generate an error because B is an INput.  Be carefull : A and B are std_logic_vectors. SIGNED or UNSIGNED, we don't know, BUT you specify use std.ieee_logic_unsigned.all. as a result a and b are treated as unsigned. I belive that IEEE.STD_LOGIC_UNSIGNED is NOT a IEEE standard.  You want to compare with "data", then you should have written "IF A < data THEN ..."

[Altera_Forum]

Thank u so much for your time. I had done exactly what u said still gave error (attached doc), but i still like to link "data" to "B" because B is what my test bench recognized. 

   --- Quote Start ---  hi, Delete the line "B = data;" : no sense and must generate an error because B is an INput.  Be carefull : A and B are std_logic_vectors. SIGNED or UNSIGNED, we don't know, BUT you specify use std.ieee_logic_unsigned.all. as a result a and b are treated as unsigned. I belive that IEEE.STD_LOGIC_UNSIGNED is NOT a IEEE standard.  You want to compare with "data", then you should have written "IF A < data THEN ..."  --- Quote End ---  

[Altera_Forum]

You moved the data assignment before the begin. You aren't allowed to do that, all the signal or variables assignments must be done after "begin". 

But why are you using a "data" signal to begin with? You can directly compare A and B in your process. Besides, using the intermediary "data" signal in your process while it isn't on the sensitivity list will give you unwanted behaviour in a VHDL simulator.  And I agree with mmTsuchi, using ieee_logic_unsigned can be dangerous, you should stick to numeric_std instead and use its "unsigned" and "signed" types instead of std_logic_vector when they represent numbers.

[Altera_Forum]

And I forgot to answer the other part of your problem.... if you need a fixed reference, then you should remove B from the ports list and make it a generic instead. That way you can even change the threshold each time you instantiate your comparator.

[Altera_Forum]

Exactly, that's where the problem lies, setting the gain... i have been experiencing logical error when the program is loaded into the device, because all the output goes high. Pls Daixiwen, can u go through my design description and corresponding code and direct me as to what to do.  

 Also i adjusted the instant of my comparator that is GENERIC MAP (WIDTH => 8192) but the output still went HIGH.  ATTACHED ARE SOME DOC     --- Quote Start ---  And I forgot to answer the other part of your problem.... if you need a fixed reference, then you should remove B from the ports list and make it a generic instead. That way you can even change the threshold each time you instantiate your comparator.  --- Quote End ---  

[Altera_Forum]

Where is your top level file? It seems that you connect your B signal to a port called "gain" but I don't see any code where you assign a value to that gain.

[Altera_Forum]

thanks for your acknowledgement, but i took the "Proposed.vhd" for my top level file. As for the gain, where do i set it? at the top level or in the actual comparator file? And syntax pls?? 

    --- Quote Start ---  Where is your top level file? It seems that you connect your B signal to a port called "gain" but I don't see any code where you assign a value to that gain.  --- Quote End ---  

[Altera_Forum]

If "proposed.vhd" is your top level file then your gain signal has been mapped to FPGA pins. Just set those pins to the threshold value that you want. If you want a fixed value for your comparator, then you can always connect the B port to a constant signal instead of "gain" when you instantiate the comparator.

[Altera_Forum]

Hello, i've been away for a while because i had to attend a conference. Really, i'm very grateful for ur assistance. 

I did exactly as u told me and i think it made some sense when i implemented. But the device (Stratix iii) output did not behave as expected (+++ this is the first time i'm using the device). So i decided to implement a simple logic(AND gate) and from my observation, apart from LED (LEDR(7)) that was assigned for output another LED (LEDR(4)) would come on alongside. In addition the 2-input AND gate seems to behave like a NAND, two HIGH = "no output", HIGH and LOW = "output", two LOW = "output". (note that "output" is shown at the assigned LED and another LED comes up alongside). But when "no output" none of them come up. Any help on this pls?  Compiler warning shows "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details".      --- Quote Start ---  If "proposed.vhd" is your top level file then your gain signal has been mapped to FPGA pins. Just set those pins to the threshold value that you want. If you want a fixed value for your comparator, then you can always connect the B port to a constant signal instead of "gain" when you instantiate the comparator.  --- Quote End ---  

[Altera_Forum]

The clue is probably in the warning. With incomplete io assignments, some pins will be assigned randomly.

[Altera_Forum]

k... but all named pins (2-input & 1-output) are assigned manually by me. the other 744 assignable pins were assigned randomly and that affects my output. How do i solve this pls? 

   --- Quote Start ---  The clue is probably in the warning. With incomplete io assignments, some pins will be assigned randomly.  --- Quote End ---  

[Altera_Forum]

To assign your input and output to FPGA pins :  

Menu Tools>"pin planer" or "assignment editor"

[Altera_Forum]

But really, i know about that and i did assigned all the pins in simple ANDgate. So i dont know which other pin is left unassigned. Could it be because of the top level file? cos i have the actual AND gate file then i top level file that created AND as a component. 

   --- Quote Start ---  To assign your input and output to FPGA pins :  Menu Tools>"pin planer" or "assignment editor"  --- Quote End ---  

[Altera_Forum]

Have you REALLY assigned inputs and outputs of your top level to your FPGA pins ? 

 Could you post the interesting parts of Quartus compilation reports ?    --- Quote Start ---  but all named pins (2-input & 1-output) are assigned manually by me. the other 744 assignable pins were assigned randomly and that affects my output. How do i solve this pls?  --- Quote End ---   Are you sure about the pins you assign ?  I don't understand what you want to mean with the second sentence because it is trivial : if you assign correctly your useful pins, you don't mind about the others (of course if there isn't any conflict)  You can set unused pins as "input tri-stated" or "output driving ground" (be careful about conflicts) in Quartus menu > ....

[Altera_Forum]

I dont really understand anything of what you've posted, as I cannot find any code with input1, input2 and output. I also do understand why you've posted a picture of some code you havent talked about. But the error is that you've put the assignment before the "begin" part of the process, but it doesnt really want to go into a process at all.