Use Multicycle path for delayed wr enabled clk?

[Altera_Forum]

I have a design that uses a write signal enabled for one clock cycle, but delayed several clock cycles after the data that I'm writing is valid. So, lets say that the data is valid at the first rising clock edge. Then the write signal pulses high 3 clock cycles later for just one cycle. How do I correctly constrain this? 

 I had been using a create_generated_clock with the the source clk divided by 2. Can I just divide that by 3 to get the delay to the start of the wr? Seems like it would not know which cycle to start on.  Or should I use a set_multicycle_path to define that? And should I somehow make it dependent on the point where the data is valid?  I'm quite new to this and would appreciate some actual examples of the statement I need to use. The syntax seems elusive to me.

[Altera_Forum]

Do You get timing errors on that? I don't understand what You have to constrain if the clock is proper and write signal is also OK?

[Altera_Forum]

It's still all on the same clock domain. If I understand correctly, you want a multicycle of 3, to say the data has been available for 3 clock cycles: 

set_multicycle_path -from <> -to <> -setup 3 set_multicycle_path -from <> -to <> -hold 2 So if your clock were 10ns, it would normally have a setup relationship of 10ns and hold of 0ns. These multicycles would make the setup 30ns and keep the hold at 0ns. This would buy slack on whatever path you specify in the -from/-to.