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Fromhell777
Beginner
477 Views

Use correct latch timing during place and route optimisation

As I understood the timing analyser treats level-sensitive latches similar to registers. When looking into the documentation the only option that you can execute to have a correct timing analysis of the latches is all the way at the end of synthesis while reporting the timing results. For this you can use the following command:

update_timing_netlist -dynamic_borrow

But in my opinion this does not solve the problem. It only provides a way to report better timing.

When you have a path from a positive register to a positive (open-high), level-sensitive latch in your design, it has a default setup clock relationship of zero clock periods, plus any time borrow value. As I understand it the "dynamic borrow" option is not used during timing optimisations while doing the place and route. This means that the result is a netlist where the tool tried to fix a setup violation that does not needed fixing and by this ignoring the other real issues in the design (hold time violations for example)

It it possible to use the "-dynamic_borrow" timing analysis option during place and route timing optimisations?

Or at least use a correct timing analysis of a latch instead of the current simplification?

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12 Replies
KennyT_Intel
Moderator
457 Views

You may take a look at:


https://www.intel.com/content/www/us/en/programmable/documentation/psq1513989797346.html -> 1.1.10.2. Time Borrowing with Latches


The way to solve it is by: set_max_time_borrow 3 [get_registers lat*]


Fromhell777
Beginner
451 Views

I haven't tried this yet but when reading the documentation I did not think this would do anything.

It states that "the time borrowing never exceeds the maximum borrow value. However, you can specify a smaller maximum borrow time with the set_max_time_borrow SDC constraint."

And before this it is said that "the Timing Analyzer automatically computes the maximum amount of time borrowing available for each latch. Typically, the maximum amount of time borrowing available is roughly equivalent to half the clock period."

So this means that by default around half the clock period is taken as borrow time and it could be further constraint with the SDC command.

It does not state that this setting will enable correct borrow time calculation during place and route timing optimisations as is clearly said in the beginning of this section: "Implementation of latch time borrowing requires that you enable Dynamic borrowing mode (update_timing_netlist -dynamic_borrow). Otherwise, the Timing Analyzer calculates zero time borrowing for latches

So when reading this paragraph I interpret it as ignoring all borrow time unless you use update_timing_netlist -dynamic_borrow (also the set_max_time_borrow SDC command would then have no effect because the maximum borrow time is zero)

Fromhell777
Beginner
444 Views

I tested it by redoing the timing analysis after synthesis with the set_max_time_borrow option and it only made the timing violations worse

KennyT_Intel
Moderator
423 Views

Is that fine that you attached the design.qar for us to investigate?

Let's us know if you want to send the design.qar privately to Intel, I will arrange for that.


Fromhell777
Beginner
419 Views

I cannot share my files due to confidentiality

KennyT_Intel
Moderator
399 Views

Kindly check your email for further conversation.


KennyT_Intel
Moderator
382 Views

Kindly check your email conversation again.


KennyT_Intel
Moderator
354 Views

We do not receive any response from you in the email. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


Fromhell777
Beginner
323 Views

Here is a simple example.

I created a circuit where data goes from a negedge flipflop, to a negative (open-low), level-sensitive latch, to a posedge flipflop.

In the timing analyser you can see that the setup time from the negedge flipflop to the negative (open-low), level-sensitive latch is as good as nothing. I expect that the setup time should be a bit less than half the clock period. Even with the "-dynamic_borrow" option I don't see anything change which I found strange.

Can you explain this?

This could have a lot of impact on the rest of the timing when the tool tries to fix this with clock skewing

Fromhell777
Beginner
282 Views

Did you already have time to look into this?

Fromhell777
Beginner
224 Views

Fromhell777
Beginner
164 Views

This is just really poor costumer support

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