Use “don’t care” statement in vhdl code

Altera_Forum · ‎10-27-2009

I will use don’t care statements in my vhdl code. Quartus 2 have more degree of freedom to reduce logic.

Example:

Case aaa IS

When 1 => bbb <= 1;

When 2 => bbb <= 2;

When others => bbb <= (others => ‘-‘); -- don't care

END Case;

My Question is: What do Quartus with don’t care statements? Will it gnd, vcc or optimise for all options?

Altera_Forum · ‎10-27-2009

try it and see. Likelyhood is that it will stick them all to '0' or '1'.

Also be carefully with dont cares. elsewhere in the code, if you evaluate b, if you did something like this:

if b(0) = '1' then....

Then if b(0) is set to '-' then the evaluation of the expresion is false.

Altera_Forum · ‎10-27-2009

I'm not aware of a std_logic value of '-', where did you get it?

Altera_Forum · ‎10-27-2009

from the std_logic_1164 package:


 -------------------------------------------------------------------    
    -- logic state system  (unresolved)
    -------------------------------------------------------------------    
    TYPE std_ulogic IS ( 'U',  -- Uninitialized
                         'X',  -- Forcing  Unknown
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance   
                         'W',  -- Weak     Unknown
                         'L',  -- Weak     0       
                         'H',  -- Weak     1       
                         '-'   -- Don't care
                       );
SUBTYPE std_logic IS resolved std_ulogic;

Its always been there

Altera_Forum · ‎10-27-2009

Thanks for your answer,

I know that I must be carefully with don’t cares. But if Quartus detect the higher degree of freedom so the can it better optimize.

Detect Quartus the higher degree of freedom and can it with the help of this better optimize?

Altera_Forum · ‎10-27-2009

Overall, I think its probably safer just not to use dont cares. I dont think its really going to help the synthesiser optimise things in any meaningful way. But by all means give it a go and see if it makes any difference.

Altera_Forum · ‎10-29-2009

I'm not sure that this is synthesizable. it might be intended just for simulation.

another question, if you don't cart about the output, why do you specifically define it? (even as don't care) just don't use the others statement.

Altera_Forum · ‎10-29-2009

Quartus will pick up Dont cares, but probably just ignore them, the same way it ignores 'X' statements.

For simulation purposes, it can be useful to specifially produce 'X's, like this example:


if en = '1' then
  q <= d;
elsif en = '0' then
  null;  --hold q
else  --catch all for unitialised input enable
  q <= 'X';
end if;

With this example, you can see that inputs are uninitialised just by looking at the output. When quartus gets hold of it it strips out the else case and just puts in a DFFE.

Altera_Forum · ‎10-29-2009

I mostly use Verilog, and I'm not familiar so much with VHDL. But if I understand the VHDL code correctly, then it certainly would help Quartus to reduce the logic.

Disregarding the HDL language, any selection logic can be optimized if you are certain that specific values would never happen at the selection input (or if you don't care about the output in that case).

--- Quote Start ---


if en = '1' then
  q <= d;
elsif en = '0' then
  null;  --hold q
else  --catch all for unitialised input enable
  q <= 'X';
end if;

--- Quote End ---

Tricky, this is not the issue that the OP is raising. You are talking about what to do when the input is 'X' (which is obviously just a simulation concept). But he is talking about something else. He is talking about using 'X' as the output in certain cases.

The idea is that you are telling Quartus that if the input has certain values, then you don't care about the output. This way, Quartus can optimize the selection logic.