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Use slow asynchronous modul in a fast synchronous mealy state machine cause timing er

Altera_Forum
Honored Contributor II
‎10-15-2013 11:45 AM
1,205 Views

Hello everyone, 

 

how can i use a slow asynchronous modul to calculate signals in one state of a fast synchronous mealy state machine without the Error Timing requirements not met? I tried to use a clock enable signal slow enough for the asynchronous modul to finish but the error still remain. 

 

thanks and regards, 

schlittk
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Altera_Forum
Honored Contributor II
‎10-15-2013 01:22 PM
459 Views

A clock enable signal doesn't change the requirements for timing closure. If the clock enable signal creates multi-cycle transfers, you have to specify them explicitely.

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Altera_Forum
Honored Contributor II
‎10-23-2013 09:02 AM
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Thank you FvM, this solves my problem.

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