Use slow asynchronous modul in a fast synchronous mealy state machine cause timing er

[Altera_Forum]

Hello everyone, 

 how can i use a slow asynchronous modul to calculate signals in one state of a fast synchronous mealy state machine without the Error Timing requirements not met? I tried to use a clock enable signal slow enough for the asynchronous modul to finish but the error still remain.  thanks and regards, schlittk

[Altera_Forum]

A clock enable signal doesn't change the requirements for timing closure. If the clock enable signal creates multi-cycle transfers, you have to specify them explicitely.

[Altera_Forum]

Thank you FvM, this solves my problem.