Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Using Return-to-Zero in simulation verilog

Altera_Forum
Honored Contributor II
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Can I use RZ digital data in my verilog simulation? 

I noticed that in Quartus two the options I have are the NRZ (non return to zero) levels. I want to use RZ data as input so that I can detect the edges to know my 1 and my 0 instead of samping for NRZ data. 

 

How can I do that? 

 

Thank you.
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Altera_Forum
Honored Contributor II
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I understand, that you wan to implement a ternary signal. It's not directly provided by verilog, but could be emulated by two binary (std_logic) signals respectively a two-bit vector.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I understand, that you wan to implement a ternary signal. It's not directly provided by verilog, but could be emulated by two binary (std_logic) signals respectively a two-bit vector. 

--- Quote End ---  

 

 

When I say RZ I mean also Manchester Enciding. 

Could you plz elaborate more?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

When I say RZ I mean also Manchester Enciding 

--- Quote End ---  

 

That's surprizing, cause Manchester code (phase encoding) and RZ (ternary signals) are clearly different coding methods to my opinion. I regard the signaling of Ethernet or ISDN as typical RZ signals. You can represent them by two digital bits after processing by a threshold detector. In simulation, you can also process an analog input signal. It depends on the simulation purpose, if this would be meaningful. Normally, simulation is a means to evaluate or predict the behaviour of a real system. If you know, how the RZ signals are treated in the real system, then you most likely also know what has to be simulated.
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Altera_Forum
Honored Contributor II
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If needed, a simple Verilog Manchester encoder can be found at  

 

http://csserver.evansville.edu/~blandfor/ueverilogtutorial.pdf 

 

page 17.
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Altera_Forum
Honored Contributor II
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what about the manchester decoder in verilog 

can any body help in this for creating the verilog code for manchester decoder which would extract the clock itself from the incomming manchester data as it is a selfclocking coding system. 

do anybody have implemented this and can i have the code for t he same
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