Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
I would like to ask if it is possible to use in a project both Verilog and VHDL files. For example: SDRAM controller in Verilog and State Machine in VHDL. I'd really appreciate some help. Michael C.
in Quartus, most certainly. for simulation you'll need to have a Simulator and license which supports mixed-languages. ModelSim-Altera Edition does not have this capability.
