Using Verilog and VHDL

[Altera_Forum]

Hello! 

I would like to ask if it is possible to use in a project both Verilog and VHDL files. For example: SDRAM controller in Verilog and State Machine in VHDL. I'd really appreciate some help. Michael C.

[Altera_Forum]

in Quartus, most certainly. for simulation you'll need to have a Simulator and license which supports mixed-languages. ModelSim-Altera Edition does not have this capability.

[Altera_Forum]

Thanks a lot for help:) 

All the best!

[Altera_Forum]

Use Modelsim SE