Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16704 Discussions

Using a project as a "black box" module for other project

EugeneF
Beginner
605 Views

There is a large Quartus II project, consisted of a multiple bdf, verilog, VHDL files. Is it possible to compile it into some single file (verilog or VHDL or some other), and then use it as a single "black box" module for other projects, without showing its internall structure?  

0 Kudos
2 Replies
Nurina
Employee
587 Views

Hello,


This should be possible. You may find these pages useful:

https://www.intel.com/content/www/us/en/docs/programmable/683796/18-1/creating-black-boxes-to-create-netlists.html

https://www.intel.com/content/www/us/en/docs/programmable/683796/18-1/creating-black-boxes-in-verilog-hdl-81234.html


And since you are using Quartus II you should be able to create VHDL/Verilog file from .bdf file.

Does this answer your question?


Regards,

Nurina


0 Kudos
Nurina
Employee
564 Views

Hello,


We do not receive any response from you on the previous question/reply/answer provided. Please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey

 

Regards,

Nurina


0 Kudos
Reply