Hi,I hope I'm at the right place. I got a Stratix III to run a control of an electrical converter. The usage of the FPGA is arround 40%. Because newer versions of Quartus II are not supporting Stratix III anymore, I have to use Quartus II 13.1. But compilation time is arround 2:30 hours. So I tried to compile the same code for a Stratix V on the newest Quartus and it took just few minutes. So my question: Is there any workaround, how to synthesize on a new Quartus version code for a Stratix III?
Furthermore, comparing compile speeds across different FPGA families (e.g. III vs V) is not going to give accurate results because the devices have inherently different architectures. For example going from 13.1 to 14.0 to 15.0 I saw barely 2-3% increase in compile time for the same large Stratix V design.
Did you have a full pinout and time specs? How full is the stratix 3? How full is the stratix 5? Many things affect compile time, not just the tool version. Tool version usually has a small effect. The biggest effect will be how full the device is and how tight the timing constraints are. Given the 5 is much larger than the 3, your design probably uses only a small %of the device resources of a device using a much faster technology.