Using sensitivity list for always block

[Altera_Forum]

Hello, I am just having a small confusion regarding best usages of sensitivity list. I understand that for combinational logic synthesis, all the signals should be included in the list (always @ (*)). However, is it a bad practice (or bad for synthesis) to have the always block be sensitive to posedge of some signal other than clk or rst ? Just an example... 

 always @ (posedge clk, posedge somesignal) begin  ... ... end  or   always @ (posedge somesignal) begin  ... ... end   thanks!

[Altera_Forum]

yes it is. You are essentially making a new clock out of logic, and thats not a good idea, as it can cause timing problems. Just stick with a single clock and use clock enables: 

 always @(posedge clk) if en = 1   //do something

[Altera_Forum]

There are applications for that, usually related to dealing with asynchronous signals. Ie, the following code toggles between "0" and "1" every time there's a rising edge om my_discriminator, which is useful to detect pulses shorter than one clock 

always @ (posedge my_discriminator_input) toggle <= !toggle;  But that's the exception rather than the norm. If you have a signal generated by synchronous logic... then don't do that. It will just create complications.

[Altera_Forum]

Hi rbugalho (http://www.alteraforum.com/forum/member.php?u=27812), yes, my signal is generated by synchronous logic. I had the intuition that it might not be a good idea and hence decided to do the following.. 

 always @ (posedge clk) begin if (mysignal == 1) //do stuff end  I hope the above is fine. Can you please elaborate how it complicates the design ?

[Altera_Forum]

Yes,the above is fine. 

 The tools do not propagate clocks through registers, so you'll need to constrain each and every of those signals as a clock in order to get valid timing analysis. Also, in FPGAs the path from a logic cell to the flip-flops' clock port is very long -- it's a pre-built clock distribution tree. Any "clock" generated clock tends to have large skews in relation to other clocks and makes timing closure harder.