Using the FIR filter megafunction correctly

[Altera_Forum]

Im using an DSP Development Kit Stratix III Edition, and I'm trying to realize a totally simple digital filter on it. The whole peripherie is working correctly (when I just switch the input through to the output, a sinus produced by a function generator can be monitored correctly by an oscilloscope at the output). But when I try to use a block made by the megafunction FIR compiler (version 8.0), I only get crap at the output - the crap looks like a rectangular function, with the same fundamental frequency as the input sinus. Is there maybe some oversteering? Does someone know what might be wrong? In the first step I just want to implement a basic low pass - but I'm not able to select the right parameters ... please help, if you can. :confused:

[Altera_Forum]

without knowing how you have setup the fir, it is hard to find the problem. 

 Your fir should have the following input signals, depending upon how you have setup the fir  here are some simple connections to "play" with the fir  clk that is the clock input use the same clock rate as you told the wizzard  reset_n i noticed that FIR sometime needs a edge here and some clock cycles within active reset to functional correctly  ast_sink_data that is you input signal n bit wide  ast_sink_valid should be 1 clk cycle long 1 for each valid ast_sink_data, see the wizzard about the ast_sink_data rate  ast_source_ready should be tied to 1 if the output can take new values, if it is 0 no output data will be produced  ast_sink_error[1:0] should be connected to 0   now with each ast_source_valid pulse, the data on ast_source_data is valid  with this basic setup the fir should run, but the result depends upon how you have setup the fir with the wizzard if you create the coeficents with the wizzard, enter the requested values   if you want you can post your fir files

[Altera_Forum]

I was already aware of what needs to be connected to the pins of the FIR (source_ready, and so on). The error must be inside the configuration of the interna of the filter. I have 14 bit inupt and 14 bit output - but how to configure the resolution? The rectangular shape of the output signal may have it's origin in alias or harmonics, resulting from wrong sample rates, or accuracy values - but I don't know exactly ...

[Altera_Forum]

could you post your fir filter that i could open it with my wizzard to have a look at it ? 

 normaly input bit width + coeficient width is the resulting output width (aproximately) if input bit width equals output bit width then there must be some kind of truncation  when you open the paramter dialog (step1) of the wizzard you can alternate the coeficient scaling and by doind so the resulting output bit width is changed.

[Altera_Forum]

Here is my filter ...

[Altera_Forum]

just opend you fir with the FIR 9.1 wizzard (no 8.0 fir installed here) 

 your signed input data with 14 bit signed width has auto scaled coefficients with 8 bit width that will lead to 24 bit full resolution bit width but the lowest 10 bits are truncated. see output specification section. your coefficient setup is a Rectangular Low Pass filter with 37 coefficients, a sample rate (clk) of 10 MHz and a cutoff frequency of 1.25MHz. of course you could feed clk width 20MHz and would get a cutoff frequency of 2.5MHz so your clk signal must be 10MHz and all signed signals lower than 1.25MHz should pass the fir. if these parameters are as desired the this fir should work and the reason for the crap you see must be outside the fir function you could set the output to full resolution and place signaltap at the output so monitor all input and output bits. to see the behavioral of your fir. with signaltap you can assign the input and output wave form as a signed signal and then you should see your input and output wave form as well as the alternating output bits.

[Altera_Forum]

I guess the problem has to be inside the filter, because everything works fine, when I just put the input_fir-line to output_fir-line (shortfusing the filter). I added some pictures of the wizard and my oscilloscope to my last post - maybe this helps a bit?

[Altera_Forum]

the output signal looks like a signed output that is displayed as unsinged output. 

the msb indicates negative numbers but as it is set, the output waveform has a positive edge and that is typical for misinterpreting signed / unsigned signals  i bet if you monitor via signaltap and assigned the signed attribute to input and output you will see two sine waves. you shpuld also see the delay you get from your fir, that should be ~37 clk cycles  how is your setup of your output dac ? unsigned ???

[Altera_Forum]

I've just tried to switch the menu item from "signed" to "unsigned" - but there was no signifikant change - exept for a more visible delay / phase shift. The only thing, that I found out, was, that the dip switch 1 inverts the signal (or not). Where can I adjust the settings of the DAC? Do my new items tell you anything?

[Altera_Forum]

hmm i need to look into the schematics of your DSP Development Kit Stratix III Edition

[Altera_Forum]

it seems that i need to install the dev kit files to have a look at the schematics, of you could post the schematics for me

[Altera_Forum]

if i have the correct schematics, the dev kit doesn't have adc and dac's they should be mounted on a hsmc connector boards, if this is correct, which one do you have or do you have the schematics for this board ?

[Altera_Forum]

I have the blue "data conversion HSMC" connected to my board.

[Altera_Forum]

You mean : 

this blue pcb (http://www.slscorp.com/pages/dc_hsmc.php) and that is the corresponding  reference manual (http://www.altera.com/literature/manual/rm_data_conversion_hsmc.pdf)  i do not see jumpers or switched to invert the signal or switch from signed to unsigned, but could it be that the adc and dac have some spi interface to parametrice the components ??  has anybody else informations about that board ?

[Altera_Forum]

have you done a simulation and SignalTap to make sure the filter itself is working? 

 did you create your own pin assignments from the dev kit's manual or start with one of the examples that comes with the kit. i think i had some trouble with this same setup and found the pin out was wrong in the manual.

[Altera_Forum]

.oO( a manual with a wrong pin out, could it be so simple ? ) 

 i wonder why the dev kit is still based upon Quartus 8.0 so no update for a while.

[Altera_Forum]

The pin-out should be working, because the design actually works when I shortfuse the filter (sinus in and sinus out). I have absolutely no more ideas to solve this problem - please, seome help! :confused::confused::confused:

[Altera_Forum]

have a look at your bitmap inside your zip file. 

there is a file called "Wirkung des Filters auf dem DSP Board.bmp" did you notice that DAC-Output is okay when you just remove the positive and negative edge ? this is a typical wave form when the sign bit is missing, or your signed values are displays unsigned. the positiv signals will form the /\ shape but when the signal goes to negative values, -1 is 0xFFF... and if this is misinterpreted, this is actual the highest value an that why you get that rising edge. now further values will count down as -2 -3 -4 showing as a \/ shape until they count back -4 -3- 2 -1 now the signal is 0 and thats why you get the negative edge displayed.   your filter is working !  but there must be some mistake in the output connection of your fir  could you post the top level where you instantiate the fir and make the connections ?

[Altera_Forum]

Here is the top level design file - if you need anything more, I will do what I can. Thank you in advance for your efforts.

[Altera_Forum]

output of your FIR called fir_a_out is connected to a DFF with its enable connected via wire "h" that is permanently vcc = 1 

i would recommend to connect the ast_source_valid of the FIR to the enable of your DFF. currently your FIR delivers output data with each clock cycle, but if you modify your FIR design this could lead to problems.  ast_sink_error[1..0] is connected to l,l but i cannot find l but l see i (hard to seperated i from l)  also your FIR has reset_n via wire h hard connected to vcc as i mentioned before, i have seen non fuctional FIR due to no reset condition for some clock cycles   you use 2 cascaded DFF to, i assume, syncronize the external adc clock rate to the internal, if you intend to do so, better place 2 instead of only 1 DFF with the internal clock  but i do not see where the fir signed output looses the signed information. could you please monitor the FIR output and the DFF via Signal Tap ? too see where the information is lost ?

[Altera_Forum]

The overall connections are copied from a employee of a secondary company working with us. He made exactly this top level design working at his desktop. The only difference is that he is using FIR Complier 9.0, and I'm using 8.0. So, the difference can only lie in the setup of the filters (from my unexperienced point of view) - we tried to make it equal (and working) via a telephone conference, but failed miserably.  

 I'm not familiar with the using of the signal tap logic analyzer. How can I place the signal probes? Can someone provide a link to a HowTo?