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VCD file generation in Modelsim: Problem with internal signals

Altera_Forum
Honored Contributor II
‎01-17-2013 09:36 AM
2,239 Views

Does VCD file created in Modelsim capture the internal signal activities in the design hierarchy..? or does it capture the signal activities of only the I/O signals..?

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Altera_Forum
Honored Contributor II
‎09-12-2015 12:12 AM
1,337 Views

Yes capture internal signals, make sure you have clock period right for PLL to lock

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