VHDL - (4-bit Adder) Combinational Logic: Hierarchical Design

Altera_Forum · ‎02-13-2016

Hi,

I'm new to VHDL and have an issue with a required project and I was hoping someone could help with my code. I'm unable to get my program to compile and not exactly sure what I'm doing wrong.

Quartus ll: EP2C35F672C6

Error (10482): VHDL error at Adder4.vhd(25): object "cIn" is used but not declared

code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Adder4 IS

GENERIC(CONSTANT N: INTEGER := 4);

PORT(

a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);

sum: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);

cOut: OUT STD_LOGIC -- Output LEDR[4]

);

END Adder4;

ARCHITECTURE imp OF Adder4 IS

COMPONENT Adder1

PORT(

a, b, cIn : in STD_LOGIC;

sum, cOut : out STD_LOGIC);

END COMPONENT;

SIGNAL carry_sig: std_logic_vector(N DOWNTO 0);

BEGIN

A1: Adder1 port map (a(0), b(0), cIn, sum(0), carry_sig(0));

A2: Adder1 port map (a(1), b(1), carry_sig(0), sum(1), carry_sig(1));

A3: Adder1 port map (a(2), b(2), carry_sig(1), sum(2), carry_sig(2));

A4: Adder1 port map (a(3), b(3), carry_sig(2), sum(3), cOut);

END imp;

Altera_Forum · ‎02-13-2016

You have connected a signal called cIn to the A1 instance of Adder1, but you have no local signal called cIn.

PS> There are 2 coding styles I would not recommend here:

1. Positional association. You can easily put signals in the wrong place. Much better to use named association:

2. I also dont like the use of components when the source is also VHDL. It means you have to maintain the same code in 2 places (and they must match). And you wont find problems until the elaboration phase (which for big designs can take a few minutes). Using direct instantiation means you can find the problem in seconds rather than minutes as the compiler checks the code directly against the entity.


A3: entity work.Adder1 --direct instantiation, no need for component.
port map (
a => a(2), 
b => b(2), 
cIn => carry_sig(1), 
sum => sum(2), 
cOut => carry_sig(2)
);

Altera_Forum · ‎02-13-2016

Hi, I want to add some comments. Avoid structural design concept in low-level elements. if you learn it, then think in this manner "okay . i tried it. let it forget until i understand top -down design". structural concept useful when some of your design files come from outside your CAD tools or you try to represent close as initial functional diagram for device. for example shared bus with several independed elements.

Altera_Forum · ‎02-13-2016

Hi Tricky,

Appreciate the info, it was really informative. Also, I really like the style of the code you provided, definitely looks much cleaner, but I'm not sure if the code would work exactly with my project. I probably should've mentioned that the project is an assignment and most of the code that I posted was provided so I'm sorta stuck with it. The code I provided was the bottom part between the BEGIN & END imp.

I tried using the code you provided just to see how it would work and I received the following error code. Sure it was something I probably did being a newbie.

Error (10481): VHDL Use Clause error at Adder4.vhd(25): design library "work" does not contain primary unit "Adder1"

Thanks

Altera_Forum · ‎02-13-2016

Thats because you need the source code for the adder1 component, and it must be compiled before adder4. If you dont have VHDL source, you must use a component, as this tells the VHDL compiler what to expect. With direct instantiation instead of checking the component it uses the entity directly.

As for the assignment, its probably one thats been used for years by an instructor/professor who is still stuck in the 1990s when it comes to technology.