VHDL Code for RISC PROCESSOR

[Altera_Forum]

I am working on 64-Bit RISC Processor. But there is a problem while linking register file and memory map file with main program. Please help me to make a code for 64-Bit RISC Processor. 

Thanks

[Altera_Forum]

Whats the problem?

[Altera_Forum]

--- Quote Start ---  Whats the problem?  --- Quote End ---    thanks for replying  when i run my program there is always a problem of port map. Xilinx gives syntax error near port. There are 2 programs one for memory mapping and another for register file. when i am trying to link them with main program then there is a problem.

[Altera_Forum]

Im sorry - my telepathy isnt working today. I suggest you read the error report - fix the code it's pointing to and then make it work. Without the actual errors or the code there is no more I can do. 

 Also - this is an Altera forum. We can help with code questions but Xilinx specific problems you need to go to the Xilinx forum: https://forums.xilinx.com/

[Altera_Forum]

--- Quote Start ---  Im sorry - my telepathy isnt working today. I suggest you read the error report - fix the code it's pointing to and then make it work. Without the actual errors or the code there is no more I can do.  Also - this is an Altera forum. We can help with code questions but Xilinx specific problems you need to go to the Xilinx forum: https://forums.xilinx.com/  --- Quote End ---    Thanks for replying sir