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VHDL FILE_OPEN does not return correct status in Quartus

Altera_Forum
Honored Contributor II
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I have a procedure in VHDL that reads a line from file and is supposed to assign signal values based on individual characters of the line. The problem i am facing is that my FILE_OPEN statement seems not be working. 

FILE_OPEN(fstatus, mem_file,"H:\memfile.dat", READ_MODE); 

 

The fstatus always have OPEN_OK if uninitialized or the value it is initialized to never changes. The complete code of the procedure is given below. 

 

library IEEE; use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.NUMERIC_STD.all; entity imem is -- instruction memory port(a: in STD_LOGIC_VECTOR(5 downto 0); rd: out STD_LOGIC_VECTOR(31 downto 0)); end; architecture behave of imem is begin process is file mem_file: TEXT; variable L, my_line: line; variable L_ch : string(1 to 8); variable ch, charac: character; variable i, index, result: integer; variable valid : boolean; -- to record whether a read is successful or not variable fstatus: FILE_OPEN_STATUS; type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0); variable mem: ramtype; begin -- initialize memory from file for i in 0 to 63 loop -- set all contents low mem(i) := (others => '0'); end loop; index := 0; FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE); report "Got status from file: '" & FILE_OPEN_STATUS'image(fstatus) & "'"; IF fstatus = OPEN_OK THEN while not endfile(mem_file) loop readline(mem_file, L); report "Got line from file: '" & L.all & "'"; result := 0; for i in 1 to 8 loop read(L, ch, valid); if (L'length = 0) then report "line empty " & integer'image(index) severity error; end if;  

 

I am using Quartus Prime Lite for Synthesis.
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Altera_Forum
Honored Contributor II
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The problem here is that Quartus does not support memory initialisation from a text file in VHDL. I raised an enhancement request for this about 8 years ago, because Xilinx XST always has allowed the use of textio to initialise a ram. Annoyingly, Quartus does support this in verilog. 

 

Just a NOTE: if it did support it - then you are doing it in the wrong way anway - it needs to be done via a function at initialisation time, not runtime in a process. 

 

If the initialisation is easily done via a function, then Quartus does support initialisation via a function (unless it involves textio) 

Otherwise your only option is to create a .mif file.
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Altera_Forum
Honored Contributor II
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PS - you didnt write a procedure, you wrote a process.

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Altera_Forum
Honored Contributor II
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Any alternate for this ? I am trying to simulate an instruction sequence that i have written in file. The contents of the file looks as follows: 

 

20020005 2003000c 2067fff7 

 

Is there any way i can read these values and assign them to signals, or changing the tool is the only option ?  

 

 

 

 

--- Quote Start ---  

The problem here is that Quartus does not support memory initialisation from a text file in VHDL. I raised an enhancement request for this about 8 years ago, because Xilinx XST always has allowed the use of textio to initialise a ram. Annoyingly, Quartus does support this in verilog. 

 

Just a NOTE: if it did support it - then you are doing it in the wrong way anway - it needs to be done via a function at initialisation time, not runtime in a process. 

 

If the initialisation is easily done via a function, then Quartus does support initialisation via a function (unless it involves textio) 

Otherwise your only option is to create a .mif file. 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
2,114 Views

 

--- Quote Start ---  

Any alternate for this ? I am trying to simulate an instruction sequence that i have written in file. The contents of the file looks as follows: 

 

20020005 2003000c 2067fff7 

 

Is there any way i can read these values and assign them to signals, or changing the tool is the only option ? 

--- Quote End ---  

 

 

you can instantiate a ram and use mif to put data there. Or write to ram from an array of constants if feasible.
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Altera_Forum
Honored Contributor II
2,114 Views

 

--- Quote Start ---  

Any alternate for this ? I am trying to simulate an instruction sequence that i have written in file. The contents of the file looks as follows: 

 

20020005 2003000c 2067fff7 

 

Is there any way i can read these values and assign them to signals, or changing the tool is the only option ? 

--- Quote End ---  

 

 

If it is only simulation, then you can use code similar to that in the original post to load the instructions.
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