VHDL: How to initialize RAM from file?

Altera_Forum · ‎12-14-2010

Good timings!

I find in internet-space this vhdl codе:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
entity ram_vhdl is
Port ( clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (9 downto 0);
din : in STD_LOGIC_VECTOR (7 downto 0);
wen : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (7 downto 0));
end ram_vhdl;
architecture Behavioral of ram_vhdl is
type TRam is array(0 to 1023) of std_logic_vector(7 downto 0);
impure function init_bram (ram_file_name : in string) return TRam is
file ramfile : text is in ram_file_name;
variable line_read : line;
variable ram_to_return : TRam;
begin
  for i in TRam'range loop
  readline(ramfile, line_read);
  read(line_read, ram_to_return(i));
  end loop;
return ram_to_return;
end function;
signal Ram : TRam := init_bram("bram1.dat");
begin
process (clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
Ram(conv_integer(addr)) <= din;
end if;
dout <= Ram(conv_integer(addr));
end if;
end process;
end Behavioral;

for initialize RAM by data from bram1.dat

But it not work in Quartus... RAM allways filled by zeros...

When i replace lines:

  for i in TRam'range loop
  readline(ramfile, line_read);
  read(line_read, ram_to_return(i));
  end loop;

by

	ram_to_return(1) := "10000001";
	ram_to_return(2) := "10000010";
	ram_to_return(3) := "10000011";

Initialization of RAM work properly.

how to initializing ram from external file in vhdl sources?

Sorry for my bad Einglish.

Altera_Forum · ‎12-14-2010

RAM initialization from files through textio library functions is only supported by ModelSim and other simulators, but not by Quartus. For synthesis, you can only use *.hex or *.mif files together with a RAM MegaFunction instance. Verilog readfunctions for binary files are supported by Quartus in constrast.

Altera_Forum · ‎12-14-2010

i use arrays, generics, and packages to initialize RAM

Altera_Forum · ‎12-15-2010

Please raise this issue as a support request with Altera. I have previously requested it, and if others do, then maybe they will finally support it (like Xilinx do!)