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Hey everyone. I was wondering if anyone would be able to help me out in making a VHDL Model for the MIPS Processor. The requirements for the VHDL code are listed below. I have spent hours trying to figure out how to implement this model to no avail. All help will be appreciated. Thanks.
1. Develop a VHDL model for the MIPS processor. The model should simulate a 4-stage (Fetch, Decode, Execute, and Write-back) pipeline design. 2. The instruction memory should be modeled as a ROM, which can be part of the Fetch unit. 3. The data memory should be modeled as a read/write Random Access Memory, which can be included within the Write-back stage. 4. The register file should be modeled as a 3-port, 32 word, Random Access Memory, which can be included within the Decode unit. 5. It should be assumed that all RAW data hazards will be handled using data forwarding between the Execute state and the Decode stage. 6. Branch hazards should be resolved statically, i.e. assume that branch delay slots are filled either with a valid instruction or with nops. 7. Implement the following R format instructions: jr, add, sub, and, or, slt, lw, sw, sb 8. Implement the following I format instructions: beq, bne lbu, addi, subi 9. Implement the following J format instructions: jal, j and nop. 10. Have the VHDL code for each pipe stage as a separate module. 11. Combine the pipe stages into a single hierarchical model and submit the VHDL code for the top-level model.Link Copied
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I built a MIPS Processor in VHDL before. You might a look: http://www.fpga4student.com/2017/09/vhdl-code-for-mips-processor.html
For the pipelined MIPS processor, I only have the Verilog version for the processor(http://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-3.html) Hope it helps.- Mark as New
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If you want to see some complex processors, start here and check out the "see also" section: https://en.wikipedia.org/wiki/leon
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