VHDL Partially Initialize in 0 a vector array

[Altera_Forum]

Im trying to create an array of vectors like shown in the code below: 

 type ram256 is array (0 to 255) of std_logic_vector (11 downto 0); signal memoria: ram256;  The problem is that, initially i only use about the first 25 vectors of the type. I need the other ones to be 0 but since they're 256 vectors in total, its too long to do it manually. Can anyone help me how to do it? I tried with for loop but when i use the test bench after, it seems like the memory its full of U's. Thank you very much in advance.

[Altera_Forum]

You can initialize all bits using 

signal memoria: ram256 := (others => (others '0'));   You can use a similar statement at the beginning of a process to set the default state and then over-ride bits.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You can initialize all bits using  signal memoria: ram256 := (others => (others '0'));   You can use a similar statement at the beginning of a process to set the default state and then over-ride bits.  Cheers, Dave  --- Quote End ---    THANK YOUU! it worked :)