I currently have some VHDL code which was written with the intended purpose of simulating waveform "A", and, via transport delay, simulating waveform "SIG" 25ns after the simulation of "A". However, the timing delay has stayed at 10ns, seemingly unable to change.
My end goal is to, in a separate set of code, delay a signal by a given amount of time, in order to allow a delay for the arrival of another signal. This code is a rough mockup to help in practicing what I hope to achieve and giving me a rough idea of what this should look like without having to use any hardware.
An image of the simulation which results from running this code is attached to the thread.
-- top level entity
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Turn_Detector_On IS
PORT (
A :in STD_LOGIC;
SIG :out STD_LOGIC) ; -- SIG, the waveform we'd like delayed, is an output
END Turn_Detector_On ;
ARCHITECTURE behaviour OF Turn_Detector_On IS
-- declare signal Tell
SIGNAL Tell: STD_LOGIC;
BEGIN
PROCESS(A)
BEGIN
if A='1'THEN
Tell <= '0' after 25 ns; -- delay tell by 25ns
ELSE
Tell <= '1' after 25 ns;
End IF;
SIG <= Tell; -- finally assign SIG the value of tell, in order to achieve delay
END PROCESS;
END behaviour ; Any help is greatly appreciated!
