VHDL example of DCFIFO

[Altera_Forum]

Does anyone have an example of a DCFIFO in VHDL they would be willing to send or post? Any unrelated code could be deleted but please include anything related to the DCFIFO. 

 Scott

[Altera_Forum]

What exactly do you want? usage can vary depending on application.

[Altera_Forum]

I posted some VHDL FIFO simulation code in this thread a while back ... 

 http://www.alteraforum.com/forum/showthread.php?t=38988  Cheers, Dave

[Altera_Forum]

Dave, 

 Thank you. dcfifo_top should be enough to get me going.  Scott

[Altera_Forum]

Dave, 

 The dcfifo is working, sort of.   lpm_showahead => "ON" but the data coming out is delayed by one read cycle no matter how many write or read clock cycles the rdreq occurs after the wrreq. If showahead is turn off the data coming out is delayed by two clock cycles. This has been verified using an external logic analyzer watching the input and output data along with the clocks and read and write requests.  The aclr line also doesn't seem to actually clear the fifo. read_aclr_synch and write_aclr_synch are both on.  Scott

[Altera_Forum]

Hey Scott, 

  --- Quote Start ---   The dcfifo is working, sort of.   lpm_showahead => "ON" but the data coming out is delayed by one read cycle no matter how many write or read clock cycles the rdreq occurs after the wrreq. If showahead is turn off the data coming out is delayed by two clock cycles. This has been verified using an external logic analyzer watching the input and output data along with the clocks and read and write requests.  The aclr line also doesn't seem to actually clear the fifo. read_aclr_synch and write_aclr_synch are both on.   --- Quote End ---   Do your simulations and logic analyzer traces match?  Which version of Quartus and Modelsim are you using? The reason I initially wrote the zip file I referred you to was that I had found an issue when simulating with Modelsim-SE versus Modelsim-ASE a long time ago (many versions of Quartus ago).  If you have a Modelsim simulation that shows the issue, or the simulations I wrote show it, I can take a look. I have multiple versions of Modelsim and Quartus installed on a machine, I could see if they give different results.  Cheers, Dave

[Altera_Forum]

Dave, 

 I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.  Scott

[Altera_Forum]

--- Quote Start ---  Dave,  I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.  Scott  --- Quote End ---    But that doesnt tell you if you have bugs in your code, which is what modelsim will tell you.  I highly suggest you write a testbench and fire modelsim up.

[Altera_Forum]

--- Quote Start ---   I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.   --- Quote End ---   You should be able to run the Modelsim simulations I provided, and then edit them to match your FIFO.   As Tricky comments, the idea here is to see if there is a difference between simulation and hardware, as that is indicative of a bug. If both simulation and hardware match, then there is more likely a misunderstanding in the implementation. This will also help you understand that its important to simulate before testing in hardware, since its much easier to probe all of the design signals.  Cheers, Dave

[Altera_Forum]

It is not that I disagree but prior to ModelSim, SignalTap and Chipscope all there was were logic analyzers and oscilloscopes. It is amazing the complex logic I got working back then using just those archaic tools. I can watch any signal that can be routed to an I/O pin. Sometimes all I had was a counter chip to use as a divider and an LED. Had to time the blink rate before the frequency counter. 

 Scott

[Altera_Forum]

Hi Scott, 

  --- Quote Start ---  It is not that I disagree but prior to ModelSim, SignalTap and Chipscope all there was were logic analyzers and oscilloscopes. It is amazing the complex logic I got working back then using just those archaic tools. I can watch any signal that can be routed to an I/O pin. Sometimes all I had was a counter chip to use as a divider and an LED. Had to time the blink rate before the frequency counter.   --- Quote End ---   I'm not arguing against using logic analyzers. Modelsim is just another tool. The advantage of Modelsim is that during development, you gain a high-level of confidence that your design "will just work" if you have a simulation that works in Modelsim, and you synthesize it, and it passes timing (based on TimeQuest constraints).   I very rarely have issues with hardware designs that have good simulations. One step in the debug of these failing systems is to look at the functional RTL simulation (basically the Modelsim simulation of the code), and then the post-place-and-route simulation (the Modelsim simulation of the HDL code generated by Quartus). If you see a discrepancy in those simulations relative to hardware, then you have something to work with.  Another important reason for creating a simulation is that it gives you the ability to show someone else your problem. I don't have access to your hardware, and so I cannot look at it. Sure, you can post a logic analyzer trace, but that does not really help much. If you post a simulation, then I'll be able to look at your code, along with how you use it, and see whether or not there is an invalid assumption in there.  Anyways, these are just comments :)   Did you get a chance to run the Modelsim simulations that I wrote? Do you see a difference in those waveforms relative to your logic analyzer traces?  Cheers, Dave

[Altera_Forum]

On top of what Dave said - without knowledge of simulation - your job prospects in FPGAs are pretty poor. Its now an essential tool for any engineer to understand and use. Without it, most of the job market will be closed to you..

[Altera_Forum]

After looking closer at the input data to the fifo it became apparent the the data was not meeting the setup time. Once that was corrected the fifo works as expected. 

 Scott

[Altera_Forum]

Hey Scott, 

  --- Quote Start ---  After looking closer at the input data to the fifo it became apparent the the data was not meeting the setup time. Once that was corrected the fifo works as expected.   --- Quote End ---   Glad to hear you solved your problem.  I still encourage you to take a look a simulation of your design :)  Cheers, Dave

[Altera_Forum]

Dave, 

 Has the convention changed? When I used to write a lot of code, 15 years ago, signals indicated if they were positive or negative logic.  For example, the dcfifo empty flag. It is active low yet the name is "rdempty". We would have called it "nRdEmpty" or something similar to show it was negative logic.  Scott

[Altera_Forum]

Hi Scott, 

  --- Quote Start ---   For example, the dcfifo empty flag. It is active low yet the name is "rdempty". We would have called it "nRdEmpty" or something similar to show it was negative logic.   --- Quote End ---   No, its not active low. The FIFO is empty when its got nothing in it, and hence the rdempty signal is high. When you write to the FIFO it goes low, as the FIFO is no longer empty.  What likely confused you is that the rdempty signal starts out high (active) after a reset, and then goes low (inactive) once written.  Cheers, Dave