VHDL global signals

[Altera_Forum]

Hi 

 I'm somewhat confused in what way quartus supports global signals.  We prototype our ASIC on a Stratix III and need some things connected to pins that on the ASIC are not. For this I defined a package containing a few signals (i.e. the crazy but for the ASIC cleaner approach).  I tried to use those on top level in two ways: - With a use clause, directly using the signals. This results in all those package signals being bidir ports of the design (how that? never said something about pin in the design), resulting in pin errors. - With the full path (work.package.signal) every time the signal is used. In this case, the synthesis fails with the following error: "Error (10780): VHDL error at titlis.vhdl(749): no support for selected name assignments to out-of-scope objects"  So in one case global signals seem supported, but are implemented weird, in the other they are not supported? Does anyone have experience with global VHDL signals and quartus?  Thanks emanuel  PS: As these are not only outputs, I can't use the LAI or similar...

[Altera_Forum]

I'm not aware of Quartus support for globals signals (signals declared in packages). The "bidir pin" point sounds strange, can you give an example how you achieved this?  

 You can specify the pins as virtual either by the assignment editor or in the VHDL text: attribute altera_attribute : string; attribute altera_attribute of virt_in: signal is "-name VIRTUAL_PIN ON";

[Altera_Forum]

Having raised a support requests before refering to global signals, I was told that Altera do not recommend using global signals, and they wont support them.

[Altera_Forum]

Hi 

 thanks for the answers. I already changed the code back to normal signals through the hierarchy. I somehow (again...) don't understand what is so difficult about implementing global signals, but I guess there's no choice.  For how I achieved the bidir pins: I think I did nothing else than the straight forward implementation of a package with signals (what by the way is supported according to the quartus help). So that is something like  ---------------- <somelibmissinghere> package foo is  signal bar : std_logic; end foo; --------------  Then I used in both top level entity and the one below ------------- library mylib; use mylib.foo.all; ------------  That would give a bidir top level pin called something like "*global*bar", where I don't remember the * parts.  Thanks and best regards, emanuel

[Altera_Forum]

From what I understand, global signals were only really intended for testbenching and debugging purposes, not actual implementation. 

 I had the idea of doing register decoding via global signals, but altera wouldnt support it. Its not too hard taking signals through hierarchies.

[Altera_Forum]

I totally agree that global signals should not be used for actual implementation things - we don't do that and I didn't plan that ;) 

 The design here is for an ASIC and everything on the FPGA is for debugging/development purposes. For that reason I would have accepted global signals on the FPGA, if that reduces the impact that FPGA elements have on the ASIC code. And that is the point where I wanted to remove a bunch of signals running through three hierarchies.  But well, Altera probably counts more on customers that do actual design on the FPGAs - and they better don't use these hacks ;)

[Altera_Forum]

would the read comments as HDL synthesis directives help you out? 

 http://quartushelp.altera.com/9.1/mergedprojects/hdl/vhdl/vhdl_file_dir_read.htm