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VHDL inout port in gate-level simulation

Altera_Forum
Honored Contributor II
3,937 Views

Hi, 

 

I have a design with an bidirectional bus (defined as inout) at the very top level.  

 

In module: HWID : inout std_logic_vector(7 downto 0); . . HWID <= data_out when (nRead = '0') else (others => 'Z'); In test bench: signal hwid : std_logic_vector(7 downto 0); . . hwid <= hwid_tb when nRead = '1' else (others => 'Z'); 

 

The code works just fine at the RTL simulation and even programmed into the device. However, if I try to run gate-level simulation, ModelSim gives the following error: 

Error: ***.vhd(94): Signal 'hwid' must have only one source since it is connected to buffer port 'HWID'. 

 

Anyone have any idea what is going on here? 

 

Thanks, 

Tobyn
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Altera_Forum
Honored Contributor II
2,536 Views

Can we see the whole code?

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Altera_Forum
Honored Contributor II
2,536 Views

This is part of a large system and test bench, so it isn't feasible to post the full code. 

 

Thanks, 

Tobyn
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Altera_Forum
Honored Contributor II
2,536 Views

Hi, 

 

I now understand what is going on. I looked at the .vho Altera compiled my design into and the inout port has been converted from inout to buffer type! It also converted all out ports to buffers as well. That explains why ModelSim complains about multiple drivers: it doesn't like anything in my test bench writing to the buffer port. 

 

ENTITY RF_module_top IS PORT ( \Rise_Edge_P(n)\ : IN std_logic := '0'; \Fall_Edge_P(n)\ : IN std_logic := '0'; HWID : BUFFER std_logic_vector(7 DOWNTO 0); nRead : IN std_logic; . . nWrite : IN std_logic ); END RF_module_top;  

 

I still don't get why Altera is doing this... Anyone know how to get around this?  

 

Thanks, 

Tobyn
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Altera_Forum
Honored Contributor II
2,536 Views

Why are you doing gate level simulation? Is there any specific reason you need to? 

Ive never done a gate level simulation in 12 years of FPGA design. With good test benches and timing specs/analysis, Ive never needed it
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Altera_Forum
Honored Contributor II
2,536 Views

Hi Tobyn, 

 

I have exactly the same issue. Did you find a solution for Quartus buffer generating? 

Because if I change manually in .vho the BUFFER to INOUT, on simulation the bus is Undefined state! 

 

Thanks,  

 

 

--- Quote Start ---  

Hi, 

 

I now understand what is going on. I looked at the .vho Altera compiled my design into and the inout port has been converted from inout to buffer type! It also converted all out ports to buffers as well. That explains why ModelSim complains about multiple drivers: it doesn't like anything in my test bench writing to the buffer port. 

 

ENTITY RF_module_top IS PORT ( \Rise_Edge_P(n)\ : IN std_logic := '0'; \Fall_Edge_P(n)\ : IN std_logic := '0'; HWID : BUFFER std_logic_vector(7 DOWNTO 0); nRead : IN std_logic; . . nWrite : IN std_logic ); END RF_module_top;  

 

I still don't get why Altera is doing this... Anyone know how to get around this?  

 

Thanks, 

Tobyn 

--- Quote End ---  

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Gianfranco9635
Beginner
214 Views

I have the same problem, but my port became output and not buffer. Anyone solve this?

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