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14961 Discussions

VHDL model for ALTCLKCTRL not generated

jrrguzman
New Contributor I
1,649 Views

Hi,

 

I'm trying to simulate a design with an ALTCLKCTRL clock buffer in it. However, I can't get QSYS to generate the VHDL simulation model. It only does generate Verilog, not matter what settings I change.

 

Is this a known issue?

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4 Replies
Vicky1
Employee
71 Views

Hi,

  1. Select "VHDL" while creating Simulation Model.
  2. Check VHDL Simulation model under Qsys_project Directory\simulation\.vhd

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

jrrguzman
New Contributor I
71 Views

Hi,

 

I made sure that was done but I can't make it nevertheless. It only generates the verilog counterpart which seems to have issues and can't be simulated either.

 

I'm using Quartus Prime Standard 17.0. Is there an issue for this in this particular version?

 

BTW, the simulation folder created is ./simulation/submodules

 

Cheers

Vicky1
Employee
71 Views

Hi,

Have you resolved the issue?

Check under simulation folder created is ./simulation/.... Instead of submodules.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

jrrguzman
New Contributor I
71 Views

Hi,

 

Well the issue is not resolved since the tool does not generate the right component model. Yes, I get the .vhd file under simulation but not the right submodule which should be generated along. I wonder if you have tried to simulate the generated IP on Modelsim.

 

However I'm moving on since I am able to work with the simulation model from v18.0.

 

Thanks for the time.

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